library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library lpm;

use lpm.lpm_components.all;

entity pos_alu is

generic( d_width : positive := 13; -- width of position vectors

d_width2 : positive := 26); -- width of position vectors squared

port( dumpdata : in std_logic; -- from main controller

clk : in std_logic; -- from external source

data_in : in std_logic_vector( d_width-1 downto 0); -- position vector of 1st pulse from detector

data1, data2, data3 : out std_logic_vector( d_width-1 downto 0) ); -- output vectors in Cartesian coordinates

end entity pos_alu;

architecture behave of pos_alu is

signal count : std_logic_vector( 2 downto 0 );

signal sp1,sp2,sp3,sp4 : std_logic_vector(d_width2-1 downto 0); -- each position value squared when stored in register

signal subr2,subr3,subr4 : std_logic_vector(d_width2-1 downto 0); -- subtraction results

signal data_sq : std_logic_vector(d_width2-1 downto 0); -- output of squarer

begin

squarer:component lpm_mult -- squarer function implemented using the lpm_mult function

generic map( LPM_WIDTHA => d_width,

LPM_WIDTHB => d_width,

LPM_WIDTHP => d_width2,

LPM_WIDTHS => d_width2 )

port map( dataa => data_in,

datab => data_in,

result => data_sq );

reg1:component lpm_ff -- contains value of z speaker squared

generic map( lpm_width => d_width2 )

port map( data => data_sq,

enable => dumpdata,

clock => clk,

q => sp4 );

reg2:component lpm_ff -- contains value of y speaker squared

generic map( lpm_width => d_width2 )

port map( data => sp4,

enable => dumpdata,

clock => clk,

q => sp3 );

reg3:component lpm_ff -- contains value of x speaker squared

generic map( lpm_width => d_width2 )

port map( data => sp3,

enable => dumpdata,

clock => clk,

q => sp2 );

reg4:component lpm_ff -- contains value of origin speaker squared

generic map( lpm_width => d_width2 )

port map( data => sp2,

enable => dumpdata,

clock => clk,

q => sp1 );

-- multiply each one together

-- then subtract and add 2 ^ 20

subr2 <= sp1 - sp2 + CONV_STD_LOGIC_VECTOR(1048576,d_width2); -- subtractions according to equations

subr3 <= sp1 - sp3 + CONV_STD_LOGIC_VECTOR(1048576,d_width2);

subr4 <= sp1 - sp4 + CONV_STD_LOGIC_VECTOR(1048576,d_width2);

-- divide by 2^11

data1 <= subr2( d_width2-3 downto 11 );

data2 <= subr3( d_width2-3 downto 11 );

data3 <= subr4( d_width2-3 downto 11 );

end architecture behave;