library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library lpm;

use lpm.lpm_components.ALL;

use work.test_pkg.all;

entity mc_uart is

port( clk : in std_logic;

CTS_comp : out std_logic;

send_req_comp : in std_logic;

data_in_comp : in std_logic_vector(7 downto 0);

ack_comp : in std_logic;

rec : in std_logic;

trans_req_comp : out std_logic;

data_out_comp : out std_logic_vector(3 downto 0);

BCDdisplay1 : out std_logic_vector(6 downto 0);

BCDdisplay2 : out std_logic_vector(6 downto 0);

sp1_out, sp2_out, sp3_out, sp4_out : out std_logic;

mic_address : out std_logic_vector(4 downto 0);

pos2_data : out std_logic_vector(12 downto 0));

end mc_uart;

architecture behavioural of mc_uart is

signal data_in : std_logic_vector(7 downto 0); --from UART

signal data_rec, ready_to_send : std_logic; --from UART

signal data_ack, data_send : std_logic; --to UART

signal data_out : std_logic_vector(7 downto 0); --to UART

signal state_bin : std_logic_vector(7 downto 0); --to BCD encoder

signal slowclk : std_logic;

signal count : std_logic_vector(5 downto 0);

signal e_go1, e_go2, e_go3, e_go4 : std_logic;

signal d_go, data_ack_d : std_logic; --to detector

signal detected_data, timeout : std_logic; --from detector

signal dumpdata : std_logic; --to pos_alu

signal posx, posy, posz : std_logic_vector(12 downto 0); --from pos_alu

signal pos1_data : std_logic_vector(12 downto 0);

begin

slowclk <= count(5);

slow_clock: process(clk)

begin

if clk'EVENT and clk = '1' then

count <= count + '1';

end if;

end process;

use_emitter : component emitter

port map( clk => clk,

sp1_go => e_go1,

sp2_go => e_go2,

sp3_go => e_go3,

sp4_go => e_go4,

sp1_out => sp1_out,

sp2_out => sp2_out,

sp3_out => sp3_out,

sp4_out => sp4_out);

use_mc: component main_controller

port map( clk => slowclk,

detected_data => detected_data,

timeout => timeout,

data_in => data_in(5 downto 0),

data_rec => data_rec,

ready_to_send => ready_to_send,

data_ack => data_ack,

data_send => data_send,

data_out => data_out,

posx => posx,

posy => posy,

posz => posz,

e_go1 => e_go1,

e_go2 => e_go2,

e_go3 => e_go3,

e_go4 => e_go4,

dumpdata => dumpdata,

data_ack_d => data_ack_d,

d_go => d_go,

mic_address => mic_address,

state_bin => state_bin);

use_uart: component uart2

port map( clk => slowclk,

data_rec => data_rec,

data_ack => data_ack,

data_in => data_in,

ready_to_send => ready_to_send,

data_send => data_send,

data_out => data_out,

CTS_comp => CTS_comp,

send_req_comp => send_req_comp,

data_in_comp => data_in_comp,

ack_comp => ack_comp,

trans_req_comp => trans_req_comp,

data_out_comp => data_out_comp);

use_detector: component detector

port map( clk => clk,

go => d_go,

data_ack => data_ack_d,

rec => rec,

done => detected_data,

timeout => timeout,

pos1 => pos1_data,

pos2 => pos2_data);

use_pos_alu: component pos_alu

port map( clk => clk,

dumpdata => dumpdata,

data_in => pos1_data,

data1 => posx,

data2 => posy,

data3 => posz);

use_bcd1: component tobcd

port map( bitin => state_bin(3 downto 0),

BCDout => BCDdisplay1);

use_bcd2: component tobcd

port map( bitin => state_bin(7 downto 4),

BCDout => BCDdisplay2);

end architecture behavioural;