library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library lpm;

use lpm.lpm_components.all;

entity emitter_block is

generic( count_width : positive := 8 );

port( clk : in std_logic;

sp_go : in std_logic; -- signal from main controller

sp_out : out std_logic ); -- output to speaker array

end entity emitter_block;

ARCHITECTURE behavioural OF emitter_block IS

type state_type is (wait_to_go,pulse1,low1,pulse2,low2); -- states for state machine

signal state : state_type;

signal cnt_high_en, cnt_low_en : std_logic; -- enable lines for the 2 counters

signal cnt_high_clr, cnt_low_clr : std_logic; -- clear lines for the 2 counters

signal cnt_high_out, cnt_low_out : std_logic_vector( count_width downto 0); -- counter count outputs

BEGIN

fsm:process(clk)

-- in this process, when "sp_go" line is enabled, one pulse is produced and held until the high

-- count reaches 315. The line then goes low for a count of 315 (low count). Finally, the line

-- will go high again for a count of 315 (high count). The default will then bring the line low.

-- This produces two pulses of equal duration and separation.

begin

if clk'EVENT and clk = '1' then

case state is

when wait_to_go =>

if sp_go = '1' then

state <= pulse1;

else

state <= wait_to_go;

end if;

when pulse1 =>

if cnt_high_out >= conv_std_logic_vector(315,9) then

state <= low1;

else

state <= pulse1;

end if;

when low1 =>

if cnt_low_out >= conv_std_logic_vector(315,9) then

state <= pulse2;

else

state <= low1;

end if;

when pulse2 =>

if cnt_high_out >= conv_std_logic_vector(315,9) then

state <= low2;

else

state <= pulse2;

end if;

when low2 =>

if sp_go = '0' then

state <= wait_to_go;

else

state <= low2;

end if;

when others =>

state <= wait_to_go;

end case;

end if;

end process;

with state select

sp_out <= '1' when pulse1,

'1' when pulse2,

'0' when others;

with state select

cnt_high_en <= '1' when pulse1,

'1' when pulse2,

'0' when others;

with state select

cnt_low_en <= '1' when low1,

'0' when others;

with state select

cnt_high_clr <= '1' when wait_to_go,

'1' when low1,

'0' when others;

with state select

cnt_low_clr <= '1' when pulse1,

'0' when others;

count_high: component lpm_counter

generic map (LPM_WIDTH => 9) --we need a count for 315 so we need 2^9 bits

port map (clock => clk,

cnt_en => cnt_high_en,

sclr => cnt_high_clr,

q => cnt_high_out);

count_low: component lpm_counter

generic map (LPM_WIDTH => 9) --we need a count for 315 so we need 2^9 bits

port map(clock => clk,

cnt_en => cnt_low_en,

sclr => cnt_low_clr,

q => cnt_low_out);

END behavioural;