library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use work.test_pkg.all;

entity emitter is

port( sp1_go, sp2_go, sp3_go, sp4_go, clk : in std_logic;

-- speaker "go" lines for each speaker from teh main controller

sp1_out, sp2_out, sp3_out, sp4_out : out std_logic );

-- speaker output lines, enabling each speaker

end entity emitter;

ARCHITECTURE behavioural OF emitter IS

BEGIN

eb1: component emitter_block -- speaker 1 in our speaker grid

port map(clk => clk,

sp_go => sp1_go,

sp_out => sp1_out);

eb2: component emitter_block -- speaker 2 in our speaker grid

port map(clk => clk,

sp_go => sp2_go,

sp_out => sp2_out);

eb3: component emitter_block -- speaker 3 in our speaker grid

port map(clk => clk,

sp_go => sp3_go,

sp_out => sp3_out);

eb4: component emitter_block -- speaker 4 in our speaker grid

port map(clk => clk,

sp_go => sp4_go,

sp_out => sp4_out);

END behavioural;