-- file output_logic.vhd
-- The is the top level code for the LCD Output

-- Input: 	Betting Factor (factorin)
--			User Hand Inputted flag (card_dealt)
--			User Action (action_1)
--			clock, reset.
--
-- Output:	LCD Instructions (LCD_codes)

-- This component takes the play action code and betting factor signals 
-- and displays them at the correct time.


library ieee; 
library work;
use work.LCD_types.all;
use ieee.std_logic_1164.all; 


-- Outputs all the data to an LCD
entity output_logic is
	port (
		factorin : in std_logic_vector(factor_bit downto 0);
		reset : in std_logic;
		clock : in std_logic;		
		card_dealt : in std_logic;
		action_1 : in std_logic_vector(action_bits-1 downto 0);
		LCD_codes : out std_logic_vector(comm_bit -1 downto 0)
	);
end entity output_logic;

architecture components of output_logic is

--	signal	card_dealt : std_logic;
--	signal	action_1 : std_logic_vector(action_bits-1 downto 0);
--	signal	factorin : std_logic_vector(factor_bit downto 0);

	component clk_div 
	generic(N: positive:= 1000);	
	port 

    	(fast_clk, reset: in std_logic; 
		 slow_clk: buffer std_logic); 
    end component clk_div; 

	
	
	-- Outputs all the data to an LCD
	component char_codes 
		port (
			factorin : in std_logic_vector(factor_bit downto 0);
			clock : in std_logic;
			card_dealt : in std_logic; -- Check whether all card have been dealt
			-- Action codes
			action_1 : in std_logic_vector(action_bits-1 downto 0);
			-- The display data
			factor: out std_logic_vector(databit-1 downto 0);
			address: out std_logic_vector(addressbit-1 downto 0);	
			datascreen: out std_logic	);
	end  component char_codes;

component LCDout 
	port (address: in std_logic_vector(addressbit-1 downto 0);--data: in display;
	reset, clock:in std_logic;
	factor: in std_logic_vector(databit-1 downto 0);
	datascreen: in std_logic;

	command: out std_logic_vector(comm_bit-2 downto 0);
	enable: out std_logic);

end component LCDout;

signal datalink: std_logic_vector(addressbit-1 downto 0);
signal datascrlink: std_logic;
signal factorlink:std_logic_vector(databit-1 downto 0);

signal slowclock:std_logic;

begin


--card_dealt <= '1';

--action_1 <= "01";
--factorin <= "01001";


--card_dealt <= '1';

--slowdown:clk_div
--port map (	fast_clk => clock,
--			reset => reset, 
--			slow_clk =>slowclock
--		); 

slowclock <= clock;

screen_choose:char_codes
	port map(
			factorin=>factorin,
			clock => slowclock,
			factor =>factorlink,
			card_dealt => card_dealt,
			-- Action codes
			action_1  => action_1,
			-- The display data
			address => datalink,
			datascreen => datascrlink);

lcd_command:LCDout 
	port map(address => datalink,
			reset=> reset,
			clock=> slowclock, 
			factor => factorlink,
			datascreen=> datascrlink,

			command=>LCD_codes(comm_bit-1 downto 1),
			enable=>LCD_codes(0));

end components;