-- file name: pbdecoder.vhd
-- protection block1
-- input : A+FAC  A+(F.A.C)(input for this block coming from the 
--		   output of firing angle calculation block).
-- input : A-FAC  A-(F.A.C)(input for this block coming from the
--         output of firing angle calculation block).
-- output: four out put A1+, A1-, B1+, B1- rom this block are 
--		   FOR1 AND REV1  and going to the scr firing forward 
--		   and reverse  buffers (all outputs of these buffers are 
--		   active low .
--		   FOR1 and REV1 are active low
------------------------------------------------------------- 		  
--    			inputs						outputs 
-------------------------------------------------------------
--		A+FAC A-FAC 	A1+		A1-		B1+		B1-
-------------------------------------------------------------	
--		0		0		1		1		1		1
--		1		0		0		1		1		0
--		0		1		1		0		0		1
--		1		1		1		1		1		1

--  I defined  the output as an scr bits ( A=,A-,B+,B- = SCROUT(3 downto 0)
--------------------------------------------------------------------	
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity pbdecoder  is

port(
		APFAC,ANFAC : in std_logic ;
		SCROUT: out std_logic_vector(3 downto 0));

end pbdecoder ;

architecture BEHAV of pbdecoder  is

begin 

SCRDECODER: process(APFAC,ANFAC)

begin
		IF APFAC = '0' THEN 
		   IF ANFAC ='0' THEN
			  SCROUT <= "1111";		-- A+,A-,B+,B- (ALL OFF)
		   ELSIF ANFAC ='1' THEN
			  SCROUT <= "1001" ;	-- A+(OFF),A-(ON),B+(ON),B-(OFF)	
			END IF ;
		ELSIF APFAC = '1' THEN
			IF ANFAC ='0' THEN
				SCROUT <= "0110" ;	-- A+(ON),A-(OFF),B+(OFF),B-(ON)
			ELSIF ANFAC ='1' THEN
				SCROUT <= "1111" ;	-- A+(OFF),A-(OFF),B+(OFF),B-(OFF)
			END IF;
		END IF ; 					 	
END PROCESS SCRDECODER;
END BEHAV ;