-- file nam : PASCRDU.VHD -- file is use to combine all the components -- INPUTS : FORCU : FORWARD INPUT FROM CONTROL UNIT --- REVCU:REVERSE INPUT FROM CONTROL UNIT --- APFADU:POSITIVE AC CYCLE INPUT FROM FIRING ANGLE DELAY MEASURING --- CIRCUIT. --- ANFADU: NEGATIVE AC CYCLE INPUT FROM FIRING ANGLE DELAY --- MEASURING CIRCUIT. --- FSCRBDATA: 4 BITS OUTPUT GOING TO MOTOR FORWARD SCR BRIDGE. --- RSCRBDATA: 4 BITS OUTPUT GOING TO MOTOR REVERSED SCR BRIDGE. -- ALL OUTPUTS ARE ACTIVE LOW -- ALL THE INPUTS ARE ACTIVE HIGH library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY PASCRDU is PORT( FORCU,REVCU,APFADU,ANFADU: IN STD_LOGIC ; FSCRBDATA,RSCRBDATA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END PASCRDU ; architecture BEHAV of PASCRDU is --COMPONENT pb1scrdout2 COMPONENT pb1so2 PORT ( FORC,REVC, APFAC, ANFAC : IN STD_LOGIC; FOR1, REV1 : OUT STD_LOGIC ); END COMPONENT ; COMPONENT pbdecoder PORT ( APFAC ,ANFAC :IN STD_LOGIC ; SCROUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT ; COMPONENT PSCRFBUFF PORT ( FORB1 : IN STD_LOGIC ; SCRDATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); FSCRDATA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT ; COMPONENT pscrrbuff PORT ( REVB1 : IN STD_LOGIC; SCRDATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); RSCRDATA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT ; SIGNAL FORBC,REVBC : STD_LOGIC; SIGNAL SCRSEL : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROTECTIONBLK: pb1so2 port map( FORC=> FORCU, REVC=> REVCU, APFAC=> APFADU, ANFAC=> ANFADU, FOR1=> FORBC, REV1=> REVBC ); SCRDECODER: pbdecoder port map( APFAC=> APFADU, ANFAC=> ANFADU, SCROUT=> SCRSEL ); FORBRIDGEBUFF: pscrfbuff port map( FORB1=> FORBC, SCRDATA=> SCRSEL, FSCRDATA=> FSCRBDATA ); REVBRIDGEBUFF: pscrrbuff port map( REVB1=> REVBC, SCRDATA=> SCRSEL, RSCRDATA=> RSCRBDATA ); END BEHAV;