--***************************************
--mux.vhd
--***************************************

LIBRARY ieee;
use ieee.std_logic_1164.all;

ENTITY mux IS
-----------------------------------
generic (in_width : positive := 4;			--input width	
		out_width : positive := 4);			--output width
------------------------------------
	PORT(
		A		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
 		B		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
		C		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
		D		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
 		E		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
		F		: IN		STD_LOGIC_VECTOR(in_width-1 downto 0);
		sel		: IN		STD_LOGIC_VECTOR(2 downto 0);
		Y		: BUFFER	STD_LOGIC_VECTOR(out_width-1 downto 0)
		);
END mux;

ARCHITECTURE behavioural OF mux IS     --architecture of the multiplexer
BEGIN

muxing: process(sel)
begin
		case sel is				
			when "000" =>				-- output signls assignment 
				Y <= A;					-- sel selection			  
			when "001" =>
				Y <= B;
			when "010" =>
				Y <= C;
			when "011" =>
				Y <= D;
			when "100" =>
				Y <= E;
			when "101" =>
				Y <= F;
			when OTHERS =>				
		end case;

end process muxing;
END behavioural;