--- 12 register 
--- fadreg2.vhd 
--- inputs: 12 bit binary data,clock(rising edge active),rest,load_reg2a
--- inouts: load_reg2b 
--- output: 12 bit binary 
--- clock freq: same as system clock. 


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity fadreg2 is
generic ( reg2_width:integer:=12);
port(

	clock,load_reg2a,load_reg2b,reset: in std_logic ;
	in_data_reg2: in std_logic_vector(reg2_width-1 downto 0);	
	data_out_reg2: out std_logic_vector(reg2_width-1 downto 0)
	);
end  fadreg2;

architecture behav  of fadreg2 is 
begin

fadreg: process(clock,in_data_reg2,reset,load_reg2a,load_reg2b)
begin 
		if rising_edge(clock) then
			if reset ='1' then
				data_out_reg2 <= "111111111111";
			elsif reset = '0' and load_reg2b ='1' and  load_reg2a ='1' then
					data_out_reg2 <= "111111111111";	
			elsif reset='0' and load_reg2a='0' and load_reg2b='1' then
					data_out_reg2 <= in_data_reg2 ;
			elsif reset ='0' and load_reg2a='1' and load_reg2b='0' then
					data_out_reg2 <= "111111111111";
			elsif reset ='0' and load_reg2a ='0' and load_reg2b='0' then
					null ;	 				 	
			end if ;
		end if ;
end process fadreg ;
end behav ;