--*******************************************************
-- DISPLAY BLOCK
--*******************************************************

LIBRARY lpm;
USE lpm.lpm_components.ALL;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dblock is
-----------------------------------------
generic (speed_width		: positive := 10;
		 seg_width			: positive := 7;
		 segen_width		: positive :=6;	
		 rpmout_width		: positive :=10);
-------------------------------------------
port (
		clock 	   	: in 		std_logic;
		reset      	: in 		std_logic;
		techo_in   	: in 		std_logic;
		usrs_speed 	: in 		std_logic_vector(speed_width-1 downto 0);
		seg_data   	: out 		std_logic_vector(seg_width-1 downto 0);
	    seg_enable  : out 		std_logic_vector(segen_width-1 downto 0);
		measspout	: out		std_logic_vector(speed_width+1 downto 0);		--node to view the BCD output for rpm
		rpmout		: buffer	std_logic_vector(rpmout_width-1 downto 0)	--node to view rpm output
	 );
end dblock;

architecture structure of dblock is

--*********************************************************
component sp_mment      -- speed measurement block
generic (rpmout_width	: positive :=10);
port    (
		clock,reset		: in	std_logic;
		tacho_input     : in    std_logic;
		rpm_out		    : out	std_logic_vector(rpmout_width-1 downto 0));
end component;
--*********************************************************
component conv			--Binary to BCD conversion
generic (speed_width: positive :=10);
port    (
		clock, reset	: in	std_logic;
		meas_sp, set_sp	: in	std_logic_vector(speed_width-1 downto 0);
		meas_spout		: out	std_logic_vector(speed_width+1 downto 0);
		set_spout		: out	std_logic_vector(speed_width+1 downto 0));
end component;
--*********************************************************
component display      -- BCD to seven segment display
generic (speed_width	: positive :=10;
		seg_width		: positive :=7;
		segen_width		: positive :=6
		);
---------------------------------------
port(	clock, reset				: in	std_logic;	
		crnt_speed, set_speed		: in	std_logic_vector(speed_width+1 downto 0);
		segdata						: out	std_logic_vector(seg_width-1 downto 0);
		enable						: out	std_logic_vector(segen_width-1 downto 0));
end component;

--**********************************************************
--signals 
--**********************************************************

signal rpm_output : std_logic_vector(rpmout_width-1 downto 0);
signal mspeed     : std_logic_vector(speed_width+1 downto 0);
signal uset_speed  : std_logic_vector(speed_width+1 downto 0);

--**********************************************************

begin

speed_measur : sp_mment
port map (
		  clock       => clock,
		  reset       => reset,
		  tacho_input => techo_in,
		  rpm_out     => rpm_output
		 );
----
rpmout <= rpm_output;
-----------------------------------------------------------
conversion: conv
port map (
	      meas_sp    => rpm_output,
		  set_sp     => usrs_speed,
		  clock      => clock,
		  reset      => reset,
		  meas_spout => mspeed,
		  set_spout  => uset_speed
         );
----
measspout <= mspeed;
----------------------------------------------------------
disp : display
port map (
		 crnt_speed   => mspeed,
		 set_speed    => uset_speed,
		 clock        => clock,
         reset        => reset,
		 segdata      => seg_data,
		 enable       => seg_enable
         );
----------------------------------------------------------
end architecture;