--*************************************************
--conv.vhd
--top level file for the bin2BCD converter module
--**************************************************

LIBRARY lpm;
USE lpm.lpm_components.ALL;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY conv IS					--Entity description
-----------------------------------------
generic (signal_width : positive := 10;
		 speed_width  :	positive := 10
		);
-----------------------------------------
	PORT(
		clock, reset		: IN	STD_LOGIC;
		meas_sp				: IN	STD_LOGIC_VECTOR(speed_width-1 downto 0);
		set_sp				: IN	STD_LOGIC_VECTOR(speed_width-1 downto 0);
		meas_spout			: OUT	STD_LOGIC_VECTOR(speed_width+1 downto 0);
		set_spout			: OUT	STD_LOGIC_VECTOR(speed_width+1 downto 0)
		);
END conv;
--*************************************************
ARCHITECTURE mixed OF conv IS		
--*************************************************
component convfsm is
		PORT(
			clock 		: IN		STD_LOGIC;
			re_set 		: IN		STD_LOGIC;
			done		: IN		STD_LOGIC;
			measrd		: BUFFER	STD_LOGIC;
			loadip		: OUT 		STD_LOGIC; 
			ack_done	: OUT 		STD_LOGIC;
			start		: OUT 		STD_LOGIC;
			sel			: OUT 		STD_LOGIC; 
			op_measrd	: OUT 		STD_LOGIC; 
			op_usr		: OUT 		STD_LOGIC
			);
end component;
--**************************************************
component mux_conv is
--------------------------------------
generic (data_width : positive := 10);
--------------------------------------
	port(
		A			: IN		STD_LOGIC_VECTOR(data_width-1 downto 0);
		B			: IN		STD_LOGIC_VECTOR(data_width-1 downto 0);
		sel			: IN		STD_LOGIC;
		Y			: BUFFER	STD_LOGIC_VECTOR(data_width-1 downto 0));
end component;
--***************************************************
component onebin2bcd is
-------------------------------------				 
generic (data_width : positive := 10;
		 BCD_width	: positive := 4);
--------------------------------------
   port(
		  	Clock 		: 	IN STD_LOGIC;
			Reset		: 	IN STD_LOGIC;
 			start 		: 	IN STD_LOGIC;
		  	Ack_done	: 	IN STD_LOGIC;
		  	Done 		: 	OUT STD_LOGIC;
		  	Data_In 	: 	IN STD_LOGIC_VECTOR		(data_width+1 downto 0);
		  	Bcd_1		:	BUFFER STD_LOGIC_VECTOR	(BCD_width-1 downto 0);
			Bcd_2		:	BUFFER STD_LOGIC_VECTOR	(BCD_width-1 downto 0);
		 	Bcd_3   	: 	BUFFER STD_LOGIC_VECTOR	(BCD_width-1 downto 0);
		  	bcd_data_out: 	out std_logic_vector 	(data_width+1 downto 0)
		);
END component;
--**************************************************
--Signals used 
--**************************************************
signal load_ip 		: std_logic;
signal tmpsel 		: std_logic;
signal tmpstart		: std_logic;
signal tmp_done		: std_logic;
signal tmp_ackdone	: std_logic;
signal op_measrd	: std_logic;
signal op_usr		: std_logic;
signal tmpmeas_sp	: STD_LOGIC_VECTOR(signal_width-1 DOWNTO 0); 
signal tmpset_sp 	: STD_LOGIC_VECTOR(signal_width-1 DOWNTO 0);
signal muxout		: STD_LOGIC_VECTOR(signal_width-1 DOWNTO 0);
signal bcd_out 		: STD_LOGIC_VECTOR(signal_width+1 DOWNTO 0);
signal tmpmuxout 	: STD_LOGIC_VECTOR(signal_width+1 DOWNTO 0);
signal pad 			: STD_LOGIC_VECTOR(signal_width-9 downto 0);
--***************************************************

BEGIN						--	mapping the components

pad <= "00";
--***************************************************
reg_measspeed: lpm_ff
--***************************************************
	generic map(LPM_WIDTH =>10)
-------------------------------
	port map(	data 	=> 	meas_sp,
				clock 	=> 	clock,
				sload 	=> 	load_ip,
				q 		=> 	tmpmeas_sp
			);
--*****************************************************		
reg_setspeed: lpm_ff
--*****************************************************
	generic map(LPM_WIDTH =>10)
--------------------------------
	port map(	data 	=> 	set_sp,
				clock 	=> 	clock,
				sload 	=> 	load_ip,
				q 		=> 	tmpset_sp
			);
--*****************************************************
comp_mux: mux_conv
--*****************************************************
	port map (	A 		=>	tmpmeas_sp,
				B 		=> 	tmpset_sp,
				sel 	=> 	tmpsel,
				Y 		=> 	muxout
			);
--*****************************************************
tmpmuxout <= pad & muxout;
--*****************************************************
comp_bin2bcd: onebin2bcd
	port map(	Clock		=>	clock,
				Reset 		=> 	reset,
				Start 		=> 	tmpstart,
				Ack_done	=> 	tmp_ackdone,
				Done 		=> 	tmp_done,
				Data_In 	=> 	tmpmuxout,
				bcd_data_out=> 	bcd_out
			);
--*****************************************************
comp_fsm: convfsm
--*****************************************************
	port map (	clock 		=> 	clock,
				re_set 		=> 	reset,
				done 		=> 	tmp_done,
				loadip 		=> 	load_ip,
				ack_done	=> 	tmp_ackdone,
				start 		=> 	tmpstart,
				sel 		=> 	tmpsel,
				op_measrd 	=>	op_measrd,
				op_usr 		=>	op_usr
			);
--*****************************************************
out_measspeed: lpm_ff
--*****************************************************
	generic map(LPM_WIDTH=>12)
------------------------------
	port map(	data	=>	bcd_out,
				clock	=>	clock,
				enable 	=> 	op_measrd,
				q 		=> 	meas_spout
			);
--*****************************************************
out_setspeed: lpm_ff
--*****************************************************
	generic map(LPM_WIDTH =>12)
-------------------------------
	port map(	data	=>	bcd_out,
				clock 	=> 	clock,
				enable 	=> 	op_usr,
				q 		=> 	set_spout
			);
-------------------------------------------------------
END mixed;