-- $Log: ethchip2.vhd,v $
-- Revision 1.4  1998/11/20 02:42:06  scaplan
-- Cleaned DOS ^M's that had gotten tagged along in last revision.
--
-- Revision 1.2  1998/11/11 07:35:14  scaplan
-- Modfications to deal with collisions and active remote CRS.
-- Simulation of the same.
--
-- Revision 1.1  1998/11/10 06:35:49  psomogyi
-- ethchip with receive/encrypt/send buffers.
--
-- Revision 1.2  1998/11/09 06:38:45  psomogyi
-- Made it simulate.
--
-- Revision 1.1  1998/11/09 04:31:09  scaplan
-- Did some simulation.
--
-- Revision 1.1  1998/10/24 18:30:14  gargus
-- initial revision.
--
-- 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

use work.esafe.all;

entity ethchip2 is
	generic (
		enc_data_width : positive := 8;		-- data width
		key_select_width : positive := 1;
		bf_data_width : positive := 64
	);

	port (
		clk : in std_logic;		-- system clock
		reset : in std_logic;		-- synchronous system reset

		enable : in std_logic;

		COL_A : in std_logic; 		-- Collision Detect
		CRS_A : in std_logic;		-- Carrier Sense

		TxC_A : in std_logic;		-- Transmit Clock (10 MHz feedback)

		TxD_A : out std_logic; 		-- Transmit Data
		TxE_A : out std_logic;		-- Transmit Enable

		RxD_A : in std_logic;		-- Recieve Data
		RxC_A : in std_logic;		-- Recieve Data Clock
	

		COL_B : in std_logic; 		-- Collision Detect
		CRS_B : in std_logic;		-- Carrier Sense

		TxC_B : in std_logic;		-- Transmit Clock (10 MHz feedback)

		TxD_B : out std_logic; 		-- Transmit Data
		TxE_B : out std_logic;		-- Transmit Enable

		RxD_B : in std_logic;		-- Recieve Data
		RxC_B : in std_logic		-- Recieve Data Clock
	);
end entity ethchip2;


architecture structural of ethchip2 is

signal ethA_recv_frame : std_logic;
signal ethA_recv_frame_data : std_logic;
signal ethA_recv_clk   : std_logic;
signal ethA_recv_data  : std_logic;
signal ethA_recv_error : std_logic;
signal ethA_send_error : std_logic;
signal ethA_send_data  : std_logic;
signal ethA_send_clk   : std_logic;
signal ethA_send_frame : std_logic;
signal ethA_crc_register : std_logic_vector(31 downto 0);

signal ethB_recv_frame : std_logic;
signal ethB_recv_frame_data : std_logic;
signal ethB_recv_clk   : std_logic;
signal ethB_recv_data  : std_logic;
signal ethB_recv_error : std_logic;
signal ethB_send_error : std_logic;
signal ethB_send_data  : std_logic;
signal ethB_send_clk   : std_logic;
signal ethB_send_frame : std_logic;
signal ethB_crc_register : std_logic_vector(31 downto 0);

signal encA_encrypt_decrypt : std_logic;
signal encA_enable : std_logic;
signal encA_enable2 : std_logic;
signal encA_start_cycle : std_logic;
signal encA_data_in : std_logic_vector(enc_data_width-1 downto 0);
signal encA_frame_in : std_logic;
signal encA_key_select : std_logic_vector(key_select_width-1 downto 0);
signal encA_done_cycle : std_logic;
signal encA_data_out : std_logic_vector(enc_data_width-1 downto 0);
signal encA_frame_out : std_logic;

signal encB_encrypt_decrypt : std_logic;
signal encB_enable : std_logic;
signal encB_enable2 : std_logic;
signal encB_start_cycle : std_logic;
signal encB_data_in : std_logic_vector(enc_data_width-1 downto 0);
signal encB_frame_in : std_logic;
signal encB_key_select : std_logic_vector(key_select_width-1 downto 0);
signal encB_done_cycle : std_logic;
signal encB_data_out : std_logic_vector(enc_data_width-1 downto 0);
signal encB_frame_out : std_logic;

begin

encB_encrypt_decrypt <= '1';
encA_encrypt_decrypt <= '0';

encB_enable2 <= encB_enable and enable;
encA_enable2 <= encA_enable and enable;

eth_rxA : eth_receive
	port map (
		COL => COL_A,
		CRS => CRS_A,

		COL_remote => COL_B,
		CRS_remote => CRS_B,

		RxD => RxD_A,
		RxC => RxC_A,

		eth_recv_frame => ethA_recv_frame,
		eth_recv_clock => ethA_recv_clk,
		eth_recv_data => ethA_recv_data,
--		eth_recv_error => ethA_recv_error,
		eth_recv_frame_data => ethA_recv_frame_data
	);
eth_txA : eth_transmit
	port map (
		COL => COL_A,
		TxC => TxC_A,

		TxD => TxD_A,
		TxE => TxE_A,

		eth_send_error => ethA_send_error,
		eth_send_data  => ethA_send_data,
		eth_send_clock => ethA_send_clk,
		eth_send_frame => ethA_send_frame,
		crc_register => ethA_crc_register
	);

eth_crcA : crc_gen
	generic map (
		crc_width => 32
	)
	port map (
		clock => TxC_A,
		reset => reset,
		input => ethA_send_frame,
		data => ethA_send_data,
 		crc_poly => ethA_crc_register
	);


eth_rxB : eth_receive
	port map (
		COL => COL_B,
		CRS => CRS_B,

		COL_remote => COL_A,
		CRS_remote => CRS_A,


		RxD => RxD_B,
		RxC => RxC_B,

		eth_recv_frame => ethB_recv_frame,
		eth_recv_clock => ethB_recv_clk,
		eth_recv_data => ethB_recv_data,
--		eth_recv_error => ethB_recv_error,
		eth_recv_frame_data => ethB_recv_frame_data
	);
eth_txB : eth_transmit
	port map (
		COL => COL_B,
		TxC => TxC_B,

		TxD => TxD_B,
		TxE => TxE_B,
		
		eth_send_error => ethB_send_error,
		eth_send_data  => ethB_send_data,
		eth_send_clock => ethB_send_clk,
		eth_send_frame => ethB_send_frame,
		crc_register => ethB_crc_register
	);

eth_crcB : crc_gen
	generic map (
		crc_width => 32
	)
	port map (
		clock => TxC_B,
		reset => reset,
		input => ethB_send_frame,
		data => ethB_send_data,
 		crc_poly => ethB_crc_register
	);

recvA : recv_buffer
	generic map (
		enc_data_width => enc_data_width,
		key_select_width => key_select_width
	)
	port map (
		recv_clk => clk,
		recv_reset => reset,

		recv_eth_data => ethA_recv_data,
		recv_eth_clk => ethA_recv_clk,
		recv_eth_frame => ethA_recv_frame,
		recv_eth_frame_data => ethA_recv_frame_data,
		recv_eth_error => ethA_recv_error,

		recv_enc_enable => encA_enable,
		recv_enc_start_cycle => encA_start_cycle,
		recv_enc_data_out => encA_data_in,
		recv_enc_frame => encA_frame_in,
		recv_enc_key_select => encA_key_select
	);

encA : encryption
	generic map (
		enc_data_width => enc_data_width,
		bf_data_width => bf_data_width,
		key_select_width => key_select_width
	)
	port map (
		enc_clk => clk,
		enc_reset => reset,

		enc_encrypt_decrypt => encA_encrypt_decrypt,
		enc_enable => encA_enable2,
		enc_start_cycle => encA_start_cycle,
		enc_data_in => encA_data_in,
		enc_frame_in => encA_frame_in,
		enc_key_select => encA_key_select,

		enc_done_cycle => encA_done_cycle,
		enc_data_out => encA_data_out,
		enc_frame_out => encA_frame_out
	);

sendA :  send_buffer
	generic map (
		enc_data_width => enc_data_width
	)
	port map (
		send_clk => clk,
		send_reset => reset,

		send_enc_done_cycle => encA_done_cycle,
		send_enc_data_in => encA_data_out,
		send_enc_frame => encA_frame_out,

		send_eth_data => ethB_send_data,
		send_eth_frame_start => ethB_send_frame,
		send_eth_error => ethB_send_error,
		send_eth_clk => ethB_send_clk
	);

recvB : recv_buffer
	generic map (
		enc_data_width => enc_data_width,
		key_select_width => key_select_width
	)
	port map (
		recv_clk => clk,
		recv_reset => reset,

		recv_eth_data => ethB_recv_data,
		recv_eth_clk => ethB_recv_clk,
		recv_eth_frame => ethB_recv_frame,
		recv_eth_frame_data => ethB_recv_frame_data,
		recv_eth_error => ethB_recv_error,

		recv_enc_enable => encB_enable,
		recv_enc_start_cycle => encB_start_cycle,
		recv_enc_data_out => encB_data_in,
		recv_enc_frame => encB_frame_in,
		recv_enc_key_select => encB_key_select
	);

encB : encryption
	generic map (
		enc_data_width => enc_data_width,
		bf_data_width => bf_data_width,
		key_select_width => key_select_width
	)
	port map (
		enc_clk => clk,
		enc_reset => reset,

		enc_encrypt_decrypt => encB_encrypt_decrypt,
		enc_enable => encB_enable2,
		enc_start_cycle => encB_start_cycle,
		enc_data_in => encB_data_in,
		enc_frame_in => encB_frame_in,
		enc_key_select => encB_key_select,

		enc_done_cycle => encB_done_cycle,
		enc_data_out => encB_data_out,
		enc_frame_out => encB_frame_out
	);

sendB :  send_buffer
	generic map (
		enc_data_width => enc_data_width
	)
	port map (
		send_clk => clk,
		send_reset => reset,

		send_enc_done_cycle => encB_done_cycle,
		send_enc_data_in => encB_data_out,
		send_enc_frame => encB_frame_out,

		send_eth_data => ethA_send_data,
		send_eth_frame_start => ethA_send_frame,
		send_eth_error => ethA_send_error,
		send_eth_clk => ethA_send_clk
	);

end structural;