-- $Log: esafe.vhd,v $ -- Revision 1.4 1998/11/11 07:35:12 scaplan -- Modfications to deal with collisions and active remote CRS. -- Simulation of the same. -- -- Revision 1.3 1998/11/10 06:37:08 psomogyi -- Updated signals -- -- Revision 1.2 1998/11/09 06:40:42 psomogyi -- First integrated (ethernet-only) simulation. -- -- Revision 1.1 1998/10/24 18:30:16 gargus -- initial revision. -- -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package esafe is component bf_control generic ( bf_data_width : positive := 64 -- data width ); port ( bfctl_data_in_a : in std_logic_vector(bf_data_width-1 downto 0); -- data to/from blowfish bfctl_data_in_b : in std_logic_vector(bf_data_width-1 downto 0); bfctl_data_in_c : in std_logic_vector(bf_data_width-1 downto 0); bfctl_data_out_a : out std_logic_vector(bf_data_width-1 downto 0); -- data to/from blowfish bfctl_data_out_b : out std_logic_vector(bf_data_width-1 downto 0); bfctl_data_out_c : out std_logic_vector(bf_data_width-1 downto 0); bfctl_req_a : in std_logic; -- asserts when data ready for blowfish bfctl_req_b : in std_logic; bfctl_req_c : in std_logic; bfctl_ready_a : out std_logic; -- asserts when blowfish data available bfctl_ready_b : out std_logic; bfctl_ready_c : out std_logic; bfctl_encrypt_decrypt : out std_logic; bfctl_start_cycle : out std_logic; bfctl_data_out : out std_logic_vector(bf_data_width-1 downto 0); -- data to blowfish bfctl_done_cycle : in std_logic; bfctl_data_in : in std_logic_vector(bf_data_width-1 downto 0) -- data from blowfish ); end component bf_control; component blowfish generic ( bf_data_width : positive := 64; -- data width bf_key_width : positive := 64; -- key width lut_data_width : positive := 32; -- data width to LUT module lut_select_width : positive := 11 -- select width to LUT module ); port ( bf_clk : in std_logic; -- clock bf_reset : in std_logic; -- reset (clears pipeline stages) bf_encrypt_decrypt : in std_logic; -- 1=encrypt, 0 = decrypt bf_start_cycle : in std_logic; -- rising edge triggers encrpyt/decrypt of bf_data_in bf_data_in : in std_logic_vector(bf_data_width-1 downto 0); -- data in bf_done_cycle : out std_logic; -- rising edge when bf_data_out is valid bf_data_out : out std_logic_vector(bf_data_width-1 downto 0); -- data out bf_lut_done_cycle : in std_logic; -- rising edge when lut is done lookup bf_lut_data_in : in std_logic_vector(lut_data_width-1 downto 0); -- data from the lut bf_lut_start_cycle : out std_logic; -- rising edge tells lut to do lookup bf_lut_select : out std_logic_vector(lut_select_width-1 downto 0) -- which entry to lookup ); end component blowfish; component encryption generic ( enc_data_width : positive := 8; -- data width bf_data_width : positive := 64; key_select_width : positive := 1 ); port ( enc_clk : in std_logic; -- clock enc_reset : in std_logic; -- reset (clears pipeline stages) enc_encrypt_decrypt : in std_logic; -- 1=encrypt, 0 = decrypt enc_enable : in std_logic; -- 1=enable encrypt/decrypt, 0=disabled (pass-through) enc_start_cycle : in std_logic; -- rising edge triggers encrpyt/decrypt of enc_data_in enc_data_in : in std_logic_vector(enc_data_width-1 downto 0); -- data in enc_frame_in : in std_logic; -- 1=start/middle of frame, 0=last data in frame enc_key_select : in std_logic_vector(key_select_width-1 downto 0); -- valid when new frame start enc_done_cycle : out std_logic; -- rising edge when enc_data_out is valid enc_data_out : out std_logic_vector(enc_data_width-1 downto 0); -- data out enc_frame_out : out std_logic -- 1=start/middle of frame, 0=last data in frame -- enc_bf_req : out std_logic; -- assert when data ready for blowfish -- enc_bf_data_out : out std_logic_vector(bf_data_width-1 downto 0); -- data to blowfish -- enc_bf_data_in : in std_logic_vector(bf_data_width-1 downto 0); -- data from blowfish -- enc_bf_ready_to : out std_logic -- asserts when blowfish data available -- enc_bf_ready_from : in std_logic -- asserts when blowfish data available -- enc_bf_encrypt_decrypt : out std_logic; -- enc_bf_key_select : out std_logic; ); end component encryption; component eth_receive port ( -- To ethernet tranciever (external signals) COL : in std_logic; -- Collision Detect: -- Active high when collision detected (TX or RX) CRS : in std_logic; -- Carrier Sense: -- Asserted on first valid high-low transmission on -- recieve pair. COL_remote : in std_logic; CRS_remote : in std_logic; -- Collision and Carrier sense from the OTHER ethernet device. -- Since we're not buffering, we need to know the state of the -- other device. RxD : in std_logic; -- Recieve Data RxC : in std_logic; -- Recieve Data Clock -- To recieve buffer eth_recv_frame : buffer std_logic; -- Hold high while receiving data eth_recv_clock : out std_logic; -- clock for data eth_recv_data : out std_logic; -- Recieve data eth_recv_error : buffer std_logic; -- notify of RxD error (1=error)e eth_recv_frame_data : buffer std_logic); end component eth_receive; component eth_transmit generic(buffersize : positive := 63; crcsize : positive := 31); port ( -- To ethernet tranciever (external signals) COL : in std_logic; -- Collision Detect: -- Active high when collision detected (TX or RX) TxC : in std_logic; -- Transmit Clock (10 MHz) TxD : out std_logic; -- Transmit Data: Sampled on rising edge of TxC TxE : out std_logic; -- Transmit Enable: Held high while sending data -- From send buffer -- eth_send_clear : out std_logic; -- clear to send eth_send_error : out std_logic; -- notify of TxD error (1=error) eth_send_data : in std_logic; -- data to send eth_send_clock : out std_logic; -- send data clock eth_send_frame : in std_logic; --start and end of frame -- From crc crc_register : in std_logic_vector(crcsize downto 0)); end component eth_transmit; component crc_gen generic (crc_width : positive := 31); port(clock, reset : in std_logic; input, data: in std_logic; crc_poly : out std_logic_vector(crc_width-1 downto 0)); end component crc_gen; component lut_access generic ( lut_data_width : positive := 32; -- data width to LUT module lut_select_width : positive := 11; -- select width to LUT module mem_data_width : positive := 8; -- data width to/from memory unit mem_address_width : positive := 16 -- address width to memory unit ); port ( lut_clk : in std_logic; -- clock lut_reset : in std_logic; -- reset lut_start_cycle : in std_logic; -- rising edge tells lut to do lookup lut_select : in std_logic_vector(lut_select_width-1 downto 0); -- which entry to lookup lut_done_cycle : out std_logic; -- rising edge when lut is done lookup lut_data_out : out std_logic_vector(lut_data_width-1 downto 0); -- data from the lut lut_mem_done_cycle : in std_logic; -- rising edge when memory unit has valid data lut_mem_data : in std_logic_vector(mem_data_width-1 downto 0); -- data from the memory unit lut_mem_start_cycle : out std_logic; -- rising edge tells memory unit to fetch data lut_mem_address : out std_logic_vector(mem_address_width-1 downto 0) -- which address to read ); end component lut_access; component memory_unit generic ( mem_data_width : positive := 8; -- data width to/from memory unit mem_address_width : positive := 16; -- address width to memory unit ram_data_width : positive := 8; -- data width to external RAM ram_address_width : positive := 16 -- address width to external RAM ); port ( mem_clk : in std_logic; -- clock mem_reset : in std_logic; -- reset mem_read_start : in std_logic; -- rising edge tells memory unit to fetch data mem_write_start : in std_logic; -- rising edge tells memory unit to write data mem_read_address : in std_logic_vector(mem_address_width-1 downto 0); -- which address to read mem_write_address : in std_logic_vector(mem_address_width-1 downto 0); -- which address to write mem_read_done : out std_logic; -- rising edge when memory unit has valid data mem_write_done : out std_logic; -- rising edge when memory unit has completed write mem_write_data : in std_logic_vector(mem_data_width-1 downto 0); -- data to the memory unit mem_read_data : out std_logic_vector(mem_data_width-1 downto 0); -- data from the memory unit mem_ram_data : in std_logic_vector(ram_data_width-1 downto 0); -- data from the external RAM mem_ram_address : out std_logic_vector(ram_address_width-1 downto 0); -- which address to read from RAM mem_ram_rw : out std_logic -- 1=read, 0=write ); end component memory_unit; component recv_buffer generic ( enc_data_width : positive := 8; -- data width key_select_width : positive := 1 ); port ( recv_clk : in std_logic; -- clock recv_reset : in std_logic; -- reset recv_eth_data : in std_logic; -- serial data from ethernet recv_eth_clk : in std_logic; -- clock for data recv_eth_frame : in std_logic; -- rising edge = start of frame, falling edge = end of frame recv_eth_frame_data : in std_logic; recv_eth_error : in std_logic; -- on end of frame, 1 = error, 0 = valid frame recv_enc_enable : out std_logic; -- enables encryption/decryption recv_enc_start_cycle : out std_logic; -- triggers the encryption recv_enc_data_out : out std_logic_vector(enc_data_width-1 downto 0); -- data to encrypt/decrypt recv_enc_frame : out std_logic; -- frame start/end recv_enc_key_select : out std_logic_vector(key_select_width-1 downto 0) -- valid when new frame starts ); end component recv_buffer; component send_buffer generic ( enc_data_width : positive := 8 -- data width ); port ( send_clk : in std_logic; -- clock send_reset : in std_logic; -- reset send_enc_done_cycle : in std_logic; -- rising edge = data available send_enc_data_in : in std_logic_vector(enc_data_width-1 downto 0); -- data from encryption send_enc_frame : in std_logic; -- frame start/end send_eth_data : out std_logic; -- serial data to ethernet send_eth_frame_start : buffer std_logic; -- rising edge = start of frame data to ethernet send_eth_error : in std_logic; -- rising edge = error sending, don't clear frame buffer send_eth_clk : in std_logic -- clock for data ); end component send_buffer; component sendbf_buffer generic ( enc_data_width : positive := 8; -- data width mem_data_width : positive := 8; -- data width to/from memory unit mem_address_width : positive := 16 -- address width to memory unit ); port ( send_clk : in std_logic; -- clock send_reset : in std_logic; -- reset send_enc_done_cycle : in std_logic; -- rising edge = data available send_enc_data_in : in std_logic_vector(enc_data_width-1 downto 0); -- data from encryption send_enc_frame : in std_logic; -- frame start/end send_buffer_new : out std_logic; -- new frame in buffer send_buffer_sent : in std_logic; -- rising edge = buffer sent send_mem_done_cycle : in std_logic; -- rising edge when memory unit has saved data send_mem_data : out std_logic_vector(mem_data_width-1 downto 0); -- data to the memory unit send_mem_start_cycle : out std_logic; -- rising edge tells memory unit to store data send_mem_address : out std_logic_vector(mem_address_width-1 downto 0) -- which address to write ); end component sendbf_buffer; component sendeth_buffer generic ( mem_data_width : positive := 8; -- data width to/from memory unit mem_address_width : positive := 16 -- address width to memory unit ); port ( send_clk : in std_logic; -- clock send_reset : in std_logic; -- reset send_eth_frame_rts : in std_logic; -- 1=can send a new frame, 0=currently sending frame send_eth_error : in std_logic; -- rising edge = error sending, don't clear frame buffer send_eth_clk : in std_logic; -- clock for data send_eth_data_ready : in std_logic; -- ready to receive data send_eth_data : out std_logic; -- serial data to ethernet send_eth_frame_start : out std_logic; -- rising edge = start of frame data to ethernet send_buffer_new : in std_logic; -- new frame in buffer send_buffer_sent : out std_logic; -- rising edge = buffer sent send_mem_done_cycle : in std_logic; -- rising edge when memory unit has valid data send_mem_data : in std_logic_vector(mem_data_width-1 downto 0); -- data from the memory unit send_mem_start_cycle : out std_logic; -- rising edge tells memory unit to fetch data send_mem_address : out std_logic_vector(mem_address_width-1 downto 0) -- which address to read ); end component sendeth_buffer; end package esafe;