Documentation

Final Report

Other Documents

• Project Proposal
• Project Specification
• Resource Requirements
• Simulation Documentation

Presentation

VHDL Code

Here are the overall stats on our project:

• Chip used: Altera EPF10K20
• Logic Cells used: 1046/1152
• Total lines of code: 2439

This is the VHDL code for the entire project. Note that we are not currently releasing the code for the Blowfish algorithm on the Web. See Canadian Export Contols on Cryptographic Software for details.

• esafe.vhd
  Package file containing component declarations.
• ethchip2.vhd
  Overall chip with ethernet send/receive and XOR encryption.
• eth_receive.vhd
  Ethernet receiver interface module.
• eth_transmit.vhd
  Ethernet transmitter interface module.
• crc_gen.vhd
  Ethernet 32-bit CRC generator.
• recv_buffer.vhd
  Bit/byte parallelizer and ethernet/system interface module.
• send_buffer.vhd
  Byte/bit serializer and system/ethernet interface module.
• encryption.vhd
  Progressive encryptor - byte-wise XOR.
• bf_control.vhd
  Blowfish arbitrator.
• blowfish.vhd
  Blowfish algorithm wrapper that handles handshaking.
• bf_enc.vhd
  Blowfish Algorithm.
• lutgen.vhd
  Blowfish Lookup-Table generator.
• bfcounter.vhd
  Simple counter.
• lut_access.vhd
  SRAM memory interface and arbitrator.

Application Notes

• Ethernet
• Blowfish Encryption
• Shared AFS Directory
• CVS
• Unix and X Windows Primer
• Emacs VHDL-Mode
• Shell Configurations