-- 
-- The Electronic Gardener
--
-- Mark Kudryk, Kim Ellis
-- 
-- Module Author: Mark Kudryk
-- Date: October 24, 1998
-- Status: Completed
--
-- Purpose: The purpose of this module is to generate an hour and minute count for 
--          use by other Electronic Gardener modules.  Knowing the frequency of the 
--          clock signal, this module detects when a second has elapsed, and from 
--          that can determine when a minute and an hour has elapsed.  The Time
--          will be given in 24-hour format.
--
-- Size: 72 Logic Cells
-- Period: 35.2 ns
-- Clock: 28.4 MHz
--


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

-- 
-- definition of entity signals/variables
--
-- FREQUENCY: This will be the frequency at which the system clock will be running at.
--            (The value provided must be in Hz (not MHz, or KHz).
-- 
-- read_write: This module is controled from the Menu State machine, which will be able to
--             set the hour and minute values.  When read_write is low, the state_machine is
--             only reading the the data; but when high, the state machine is setting the values,
--			   and this module will be forbidden from changing them during this time.
--
-- hour: 24 hour count.
--
-- minute: 60 minute count.

entity time is
	generic (FREQUENCY: positive := 10000); 
	port (clock, reset: in std_logic;
		  new_time: in std_logic;
		  new_hour: in std_logic_vector (4 downto 0);
		  new_minute: in std_logic_vector (5 downto 0);
		  hour: buffer std_logic_vector (4 downto 0);
		  minutes: out std_logic_vector (5 downto 0);
		  second_pulse: out std_logic);
end entity time;

architecture behaviour of time is

component mux_test is
	generic (width: positive := 8);
	port(data0, data1: in std_logic_vector (width-1 downto 0);
	     choose: in std_logic;
	     output: out std_logic_vector(width - 1 downto 0));
end component mux_test;

component datareg is
	generic (WIDTH :positive := 8);
	port (data_in: in std_logic_vector(WIDTH-1 downto 0);
		  reset, latch: in std_logic;
		  data_out: out std_logic_vector(WIDTH-1 downto 0));
end component datareg;

component increment is
	generic (width: positive:= 8);
	port (data_in: in std_logic_vector(width-1 downto 0);
		  data_out: out std_logic_vector(width-1 downto 0));
end component increment;

component comp is
	generic(width: positive :=8;
			threshold: integer := 60);
	port(data_in: in std_logic_vector(width-1 downto 0);
		 equal: out std_logic);
end component comp;

component signal_hold is
	port (signal_in: in std_logic;
		  reset, latch: in std_logic;
		  signal_out: out std_logic);
end component signal_hold;


signal seconds, minute, hours, midnight: std_logic; 
signal sig1, sig2, sig3, sig4, sig5, sig6, sig7, sig8, sig9: std_logic;
signal sig10, sig11, sig12, sig13, sig14: std_logic;
signal comp_minute, comp_hour, comp_midnight: std_logic;
signal line1, line2, line3, line4, line5: std_logic_vector (5 downto 0);
signal line6, line7, line8: std_logic_vector (4 downto 0);


begin
	
	
	time_incs: component increment
		generic map (width => 6)
	 	port map (data_in => line2,
				  data_out => line1);

	time_comps: component comp
		generic map (width => 6,
			         threshold => 61)
		port map (data_in => line1,
		          equal => comp_minute);

	time_comps_hold: component signal_hold
		port map (signal_in =>comp_minute,
		  		  reset => reset, 
				  latch => clock,
		  		  signal_out => minute);

	time_datas: component datareg
		generic map (WIDTH => 6)
		port map (data_in =>line1,
		  		  reset => sig2, 
				  latch => sig4,
		  		  data_out => line2);

	sig1 <= minute and seconds;
	sig2 <= sig1 or reset;
	sig3 <= not minute;
	sig4 <= sig3 and seconds;


	time_incm: component increment
		generic map (width => 6)
	 	port map (data_in => line5,
				  data_out => line3);

	time_compm: component comp
		generic map (width => 6,
			         threshold => 61)
		port map (data_in => line4,
		          equal => comp_hour);

	time_compm_hold: component signal_hold
		port map (signal_in =>comp_hour,
		  		  reset => reset, 
				  latch => clock,
		  		  signal_out => hours);

	time_datam: component datareg
		generic map (WIDTH => 6)
		port map (data_in =>line4,
		  		  reset => sig6, 
				  latch => sig9,
		  		  data_out => line5);

	timer_mux1: component mux_test
		generic map(width => 6)
		port map(data0 => line3,
			     data1 => new_minute,
			     choose => new_time,
	     	     output => line4);

	sig5 <= minute and hours;
	sig6 <= sig5 or reset;
	sig7 <= not hours;
	sig8 <= sig7 and minute;
	sig9 <= sig8 or new_time;
	minutes <= line5;

	time_inch: component increment
		generic map (width => 5)
	 	port map (data_in => line8,
				  data_out => line6);

	time_comph: component comp
		generic map (width => 5,
			         threshold => 25)
		port map (data_in => line7,
		          equal => comp_midnight);

	time_comph_hold: component signal_hold
		port map (signal_in =>comp_midnight,
		  		  reset => reset, 
				  latch => clock,
		  		  signal_out => midnight);


	time_datah: component datareg
		generic map (WIDTH => 5)
		port map (data_in =>line7,
		  		  reset => sig11, 
				  latch => sig14,
		  		  data_out => line8);

	timer_mux2: component mux_test
		generic map(width => 5)
		port map(data0 => line6,
			     data1 => new_hour,
			     choose => new_time,
	     	     output => line7);

	sig10 <= midnight and hours;
	sig11 <= sig10 or reset;
	sig12 <= not midnight;
	sig13 <= sig12 and hours;
	sig14 <= sig13 or new_time;
	hour <= line8;

	second_pulse <= seconds;
		  
	find_seconds: process(reset, clock)

	variable pulse_counter: natural range 0 to 2**14-1;
	
	begin

		if reset = '1' then

			pulse_counter := 0;
			seconds <= '0';
			
		elsif rising_edge(clock) then

			if pulse_counter < (FREQUENCY - 1) then
				pulse_counter := pulse_counter + 1;
				seconds <= '0';
			else
				seconds <= '1';
				pulse_counter := 0;
			end if;

		end if;

	end process find_seconds;

end architecture behaviour;