-- The Electronic Gardener
-- 
-- Mark Kudryk, Kim Ellis
--
-- System Clock Converter
--
-- This module converts the Altera UP1 25.175 MHz clock signal
-- into an approximate 10 kHz clock signal.
--
-- 21 logic cells
-- 51.81 MHz
-- 19.3 ns
--
--

library ieee;
use ieee.std_logic_1164.all;

entity internal_clock is
	port (up1_clock: in std_logic;
		  reset: in std_logic;
		  eg_clock: out std_logic);
end entity internal_clock;

architecture behaviour of internal_clock is

constant half_cycle: natural := 1259;
type state_type is (low, high);
signal state: state_type;

begin

	convert: process (up1_clock, reset)

	variable count: natural range 0 to (2**11)-1;

	begin

		if reset = '1' then
			eg_clock <= '0';
			state <= low;
		elsif rising_edge(up1_clock) then	

			case (state) is
				when low =>
					if count = half_cycle then
						count := 0;
						eg_clock <= '1';
						state <= high;
					else
						count := count + 1;
					end if;
				when high =>
					if count = half_cycle then
						count := 0;
						eg_clock <= '0';
						state <= low;
					else
						count := count + 1;
					end if;
			end case;
		end if;
	end process convert;

end architecture behaviour;