library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--file which calculates the wind speed

entity windspeed is

  generic(windspeedwidth: positive:= 4; bigcounterwidth :positive :=4);
  port(clock, sensor1, sensor2: in std_logic;
	 clk_en: in std_logic;
	 cnt_en: in std_logic;
	 sclr: in std_logic;
	 windq1: out std_logic_vector(2* windspeedwidth-1 downto 0);
	 windtq10 : out std_logic_vector(2* windspeedwidth-1 downto 0);
	 windhq100: out std_logic_vector(2* windspeedwidth-1 downto 0));
end entity;

architecture behaviour of windspeed is 

--instantiates a debounce, a bigcounter and a downcounter file

component debounce 
	port(clock, sensor1, sensor2: in std_logic;
		debounced: out std_logic);
end component;

component bigcounter is
	generic(Width: positive:= 4 );
	port(
	 clock: in std_logic;
	 clk_en: in std_logic;
	 cnt_en: in std_logic;
	 sclr: in std_logic;
	 q1: OUT STD_LOGIC_VECTOR(Width -1 DOWNTO 0); 
	 tq10: OUT STD_LOGIC_VECTOR(Width -1 DOWNTO 0); 
	 hq100: OUT STD_LOGIC_VECTOR(Width -1 DOWNTO 0)
	);
end component;

component downcounter is
	generic(Width: positive:= 8);
	port(
	 clock: in std_logic;
	 clk_en: in std_logic;
	 cnt_en: in std_logic;
	 sload: in std_logic;
	 data : in std_logic_vector(Width * 4 -1 downto 0);
	 Complete: out std_logic);
end component;

signal debounce1: std_logic;
signal complete: std_logic;
signal q1, tq10, hq100: std_logic_vector(bigcounterwidth-1 downto 0);
signal resetcounter: std_logic;
signal sload : std_logic;
signal comparision : std_logic := '1';
signal datadowncounter: std_logic_vector(31 downto 0);  -- := "00000000000111101000010010000000" for 20 MHz clock;

begin

--port maps signals from the components to the windspeed module

	debouncesignal: debounce port map(
		clock => clock,
		sensor1 => sensor1,
		sensor2 => sensor2,
		debounced => debounce1);

	calculation: bigcounter port map(
			clock => clock,
			clk_en => clk_en,
			cnt_en => debounce1,
			sclr=> resetcounter,
			q1 => q1,
			tq10 => tq10,
			hq100 => hq100);

	calculation2: downcounter port map(
			clock => clock,
			clk_en => clk_en,
			cnt_en => cnt_en,
			sload => sload,
			data => datadowncounter,		
			Complete => complete);


	changingstate: process(clock, complete, sload, datadowncounter)

	begin

-- rem'd out for testing purposes
-- following line sets counter for proper operation @ 20MHz CLOCK with 10 pulses per KPH of wind speed per second 
--		datadowncounter <= "00000000000111101000010010000000";
-- following line sets counter for proper operation @ 25.175MHz CLOCK with 10 pulses per KPH of wind speed per second 
		datadowncounter <= "00000000001001100110100111111100";
-- rem out following line for proper operation
--		datadowncounter <= "00000000000000000000001000000000";
		sload <= complete;
		resetcounter <= sload or sclr;

		--converts numbers to ascii

		if rising_edge(clock) then
			if complete = '1' then 
				windq1(7 downto 4) <= "0011";
				windq1(3 downto 0)	<= q1;
				windtq10(7 downto 4) <= "0011";
				windtq10(3 downto 0) <= tq10;
				windhq100(7 downto 4) <= "0011";
				windhq100 (3 downto 0) <= hq100;
--				sload <= complete;
	--		else
		--		sload <= '0';
			end if;			
		end if;
	end process changingstate;

end behaviour;