library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;

--used in the wind speed module,
--counts down to zero from a predetermined number (set in the 
--wind speed module)

entity downcounter is
	generic(Width: positive:= 8 );
	port(
	 clock: in std_logic;
	 clk_en: in std_logic;
	 cnt_en: in std_logic;
	 sload: in std_logic;
	 data : in std_logic_vector(Width * 4 -1 downto 0);
 
	Complete: out std_logic);
end downcounter;

architecture calculation of downcounter is

signal values1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal values2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal values3 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal values4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal carry3 : STD_LOGIC;
signal carry4 : STD_LOGIC;
signal DOWN : std_logic;
begin

--counts down using four counters (rather than one), because the chip
--can do the work more efficiently

StartCount1 : lpm_counter
   GENERIC MAP (LPM_WIDTH => Width,
	  LPM_TYPE => L_COUNTER)
   PORT MAP ( clock=> clock,
      clk_en=> clk_en,
      cnt_en=> cnt_en,
	  updown=> DOWN,
	  sload=> sload,
	  eq=> values1,
 --     q => q1,
	  data => data(Width -1 downto 0 ));


StartCount2 : lpm_counter
   GENERIC MAP (LPM_WIDTH => Width,
	  LPM_TYPE => L_COUNTER)
   PORT MAP ( clock=> clock,
      clk_en=> clk_en,
      cnt_en=> values1(0),
	  updown=> DOWN,
	  sload=> sload,
	  eq=> values2,
 --     q => q1,
	  data => data(Width * 2 -1 downto Width ));


StartCount3 : lpm_counter
   GENERIC MAP (LPM_WIDTH => Width,
	  LPM_TYPE => L_COUNTER)
   PORT MAP ( clock=> clock,
      clk_en=> clk_en,
      cnt_en=> carry3,
	  updown=> DOWN,
	  sload=> sload,
	  eq=> values3,
 --     q => q1,
	  data => data(Width * 3 -1 downto Width * 2 ));


StartCount4 : lpm_counter
   GENERIC MAP (LPM_WIDTH => Width,
	  LPM_TYPE => L_COUNTER)
   PORT MAP ( clock=> clock,
      clk_en=> clk_en,
      cnt_en=> carry4,
	  updown=> DOWN,
	  sload=> sload,
	  eq=> values4,
 --     q => q1,
	  data => data(Width * 4 -1 downto Width * 3 ));

	--state machine of how the counters should count downt


	completionstate: process(clock)
	
	begin 
		
		DOWN <= '0';
		if values2(0) = '1' and values1(0) = '1' then
			carry3 <= '1';
		else
			carry3 <= '0';
		end if;
		
		if values3(0) = '1' and values2(0) = '1' and values1(0) = '1' then
			carry4 <= '1';
		else
			carry4 <= '0';
		end if;

--		if rising_edge(clock) then
			if values4(0) = '1' and values3(0) = '1' and values2(0) = '1' then
				Complete <= values1(0);
			else
				Complete <= '0';
			end if;
--		end if;
	end process completionstate;
	
end calculation;