ARKANOID
EE 552 Project Final Report
Tyler Brandon, Kevin Lister, Chris Blasko
ABSTRACT
When we set out on this project we decided to start with a fairly simple concept, based on the classic Arkanoid game, which we could expand on as time allowed. Due to the complexity of the code that we developed, we have scaled back some of our original objectives in some areas. However, we have added additional features in other portions of the system, exceeding our original design parameters.
Originally we set about designing a system that contained the following features and controls:
After code development and hardware configuration, we realized that some of our original features would be unrealizable with the current system. Making the necessary changes, we developed a system with the following features :
This project was designed into four modules. The game module (ark.vhd), the display module (draw.vhd), the sound module (beep.vhd), and the chip module (arkanoid.vhd). All entities compile, simulate and have been verified in hardware.
ARKANOID OVERVIEW
Our chip implements a hardware version of Arkanoid. The object of the game is to remove all of the blocks of the screen by bouncing a ball off of each block. The ball is bounced off a paddle controlled by the user. Two push-buttons on the Altera board control the horizontal movement of the paddle. Originally, the ball is connected to the paddle and is released when both push-buttons are pressed. The ball can bounce off of the roof, walls, blocks, or paddle. When the ball hits the roof or walls, the ball reverses direction. If the ball hits the paddle, it bounces back at a speed and direction determined by where the ball hits the paddle. If the ball hits a block, the ball rebounds and the block is removed. When all the blocks are removed, the next level begins. If the ball touches the bottom of the screen, a life is lost. When a player has lost all his lives, the game is over.
FEATURE DESCRIPTION
BLOCK DIAGRAM
INTERFACE DESCRIPTIONS
MODULE DESCRIPTIONS
ARKANOID:
Arkanoid is the top-level component. It instantiates the Ark, Draw, and Beep components. This component takes in the clock, reset, move_left, and move_right signals. The signals Red, Green, Blue, Horiz_sync, and Vert_sync control the video display. The sound signal creates a sound when a collision is detected.
ARK:
Ark is the game component. It initializes the blocks in memory, and rewrites the blocks based upon the game logic. Once the memory has been loaded, the game enters game mode. Any collision with blocks is detected, and the ball rebounds. The block is removed from memory and a collision signal is sent if a collision is detected. A "blocks_gone" signal starts the next level. If the ball hits the walls it rebounds. If the hits the paddle, its speed changes based on where it hit the paddle. If the ball hits the bottom of the screen a life is lost. Once all a players lives is lost, the game is over. The position of the paddle and ball is sent to the draw component.
DRAW:
The draw signal is responsible for the video display. At the start of the drawing process, the coordinates of the ball and paddle are calculated. Then the drawing process begins. The timing of the monitor is controlled by the clock signal. A counter is used to count the row and column of the electron beam. If the electron beam passes an object, the color of the pixel is changed. If no blocks are drawn during the drawing process, a "blocks_gone" signal is sent to the Ark component.
BEEP:
If a collision is detected in the game code, the sound signal oscillates at 30Hz for 0.1s. The schematic for the external audio circuit can be found in Appendix A. The VHDL code for all of the components can be found in Appendix B.
CIRCUIT TIMING
The vertical sync for the VGA monitor runs at a 60Hz cycle (active low). To accommodate the write time of the video display and the memory requirements all game functions occur during the vertical reset. When the vertical sync pulse goes low, the calculations for collisions, redrawing, and sound are made. When the vertical sync pulse goes high, the drawing routine takes over and draws the results of the recently updated game on the monitor.
DESIGN DETAILS
We implemented our design using a FLEX 10K20C240-4 board. We chose this board because it had an adequate number of logic cells and was readily available. The embedded memory was also useful for our design. By ignoring the five least significant bits of the horizontal counter, the address remains constant for exactly 32 pixels. Similarly, the four least significant bits of the vertical counter are ignored, giving the block a defined height. If an address contains a ‘1’, then a block that is 32X16 pixels will be drawn on the screen. Otherwise, nothing will be drawn on the screen. A block can be erase by assigning its address the value ‘0’.
There were several problems we encountered with our code. In most cases, we found ways to work around or solve these problems, however, with others, the size of the code or the complexity of the problem forced us to abandon the feature.
Problem #1: Synchronous Reset not properly being set.
Solution: Made an asynchronous reset
Problem #2: Code not responding to mouse inputs.
Solution: Replaced mouse feature with push button input
Problem #3: Level not resetting upon completion.
Problem #4: Instead of counting blocks to see when we finished the level, we set a flag to go high when the draw component indicated no blocks drawn. We then reset the level on that flag.
Problem #5: Insufficient room for multiple levels.
Solution: Only one level was set.
TESTING
Our design was simulated using the Maxplus2 simulator. We have included four simulation waveforms in Appendix C.
The design was implemented in hardware and operated correctly. There are a few bugs that we hope to repair promptly: occasionally a block will not disappear on the first collision, the blocks occasionally initialize incorrectly, and the game occasionally doesn’t reload when all of the blocks have been removed.
IC DATA SHEET
As stated above, our code came very close to utilizing the full capacity of the Altera chip. Due to careful optimization, we have managed to include these features:
Our design, including this feature set, required 923/1152 logic cells (80% capacity). The logic cell usage for each component is shown in Fig. 1.
File # of Logic Cells
ARKANOID.VHD 923
ARK.VHD 588
DRAW.VHD 232
BEEP.VHD 102
The maximum and minimum clock speed is 25.175 MHz. VGA standards, built into monitors, dictate a clock speed of 25.175MHz to operate in 640x480 resolution at a 60Hz refresh cycle. The generated 60Hz refresh cycle and the main clock (25.175MHz) are used to clock various processes within the game. As the program interfaces with humans, it is required to maintain a certain "playability", and thus it would not be beneficial to increase or decrease the clocking.
Setting the pin assignments was relatively easy, as the system is largely self-contained within the Altera board. The pin assignments are shown in Fig. 2.
DEVICE = EPF10K20RC240-4;
move_left : INPUT_PIN = 28 -Flex Push Button 1
move_right : INPUT_PIN = 29 -Flex Push button 2
reset : INPUT_PIN = 41 -Flex Switch 1
clock : INPUT_PIN = 91 -Clock pin
sound : OUTPUT_PIN = 101 -Flex_Expan_A hole 56
Vert_Sync : OUTPUT_PIN = 239 -Monitor port
Horiz_Sync : OUTPUT_PIN = 240 -Monitor Port
Blue : OUTPUT_PIN = 238 -Monitor Port
Green : OUTPUT_PIN = 237 -Monitor Port
Red : OUTPUT_PIN = 236 -Monitor Port
Figure 2. Arkanoid Pin Assignments