--------------------------------------------------------------------------------
-- Oscillator.vhd
--
-- Generates a 1010 square wave at the specified frequency when enable = '1'.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
 
library work;
use work.Counter_Package.all;
use work.Time_Package.all;

entity Oscillator is
--    generic(
--      frequency: std_logic_vector(ONE_SEC_25MHZ_WIDTH-1 downto 0) := "0000000000110001001010111"
--    );
    port(
      clock: in std_logic;
      enable: in std_logic;
      output_signal: out std_logic
    );
end Oscillator;

architecture structural of Oscillator is
--signal frequency: std_logic_vector (ONE_SEC_25MHZ_WIDTH-1 downto 0);
signal frequency:
  std_logic_vector(3 downto 0);

type state_type is (waiting, output1, output2, output3, output4);

signal NextState : state_type;
signal load_enable, reset, overflow, count_enable : std_logic;
--signal min, max, count, input : std_logic_vector (ONE_SEC_25MHZ_WIDTH-1 downto 0);
signal min, count, input : std_logic_vector (3 downto 0);

begin
  reset <= '0';
  load_enable <= '0';
  min <= (others => '0');
  input <= (others => '0');
  frequency <= "0111";
  LastForSomeTime : counter
   port map(
      clock => clock,
      reset => reset,
      overflow => overflow,
      count_enable => count_enable,
      load_enable => load_enable,
      input_count => input,
      Min_Count => min,
      Max_Count => frequency,
      count => count
    );

  oscillate : process (clock) is
  begin
    if rising_edge (clock) then
      case NextState is
        when waiting =>
          if enable = '1' then
            NextState <= output1;
--            count_enable <= '1';       
          else 
            NextState <= waiting;
          end if;

        when output1 =>
          if enable = '1' then
            if overflow = '1' then
              NextState <= output2;
            else
              NextState <= output1;
            end if;
          else
            NextState <= waiting;
          end if;

        when output2 =>
          if enable = '1' then
            if overflow = '1' then
              NextState <= output3;
            else
              NextState <= output2;
            end if;
          else
            NextState <= waiting;
          end if;

        when output3 =>
          if enable = '1' then
            if overflow = '1' then
              NextState <= output4;
            else 
              NextState <= output3;
            end if;
          else
            NextState <= waiting;
          end if;

       when output4 =>
          if enable = '1' then     
            if overflow = '1' then
              NextState <= waiting;
            else 
              NextState <= output4;
            end if;
          else
            NextState <= waiting;
          end if;

        when others =>
          NextState <= waiting;
      end case;
    end if;
   end process oscillate;  
  with NextState select
	 output_signal <= '1' when output1 | output3,
				'0' when others;
  with NextState select
	 count_enable  <= '1' when output1 | output2 |output3 |output4,
				'0' when others;
end structural;