--------------------------------------------------------------------------------
-- ClockGenerator.vhd
-- clock generator
-- created: 1998 Oct 3, Sydney Tang
--
-- 52 cells (4%), 48.3ns, 20.70MHz (7.21)
--
-- The system clock generates a 1 Hz clock for time/date counting,
-- and a system clock whose period is an integral multiple of the 25.175MHz one.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.Time_Package.all;
use work.Counter_Package.all;

entity ClockGenerator is
    port(
      clock_at_25175000_Hz: in std_logic;     -- 25.175 MHz clock
      SystemClock: out std_logic;             -- primary system clock
      OneSecondClock: out std_logic           -- one-second clock
    );
end ClockGenerator;


architecture structural of ClockGenerator is

  signal OneSecondStartValue, OneSecondEndValue, OneSecondCounterOutput:
    std_logic_vector(ONE_SEC_25MHZ_WIDTH-1 downto 0);

  signal SystemClockStartValue, SystemClockEndValue, SystemClockCounterOutput:
    std_logic_vector(SYS_CLOCK_COUNTER_WIDTH-1 downto 0);

  signal systemClockOverflow: std_logic;
  signal SystemClockValue: std_logic;
  signal InvertedSystemClock: std_logic;

  signal high, low: std_logic;

begin

  SystemClock <= SystemClockValue;
  InvertedSystemClock <= not SystemClockValue;

  high <= '1';
  low <= '0';

  OneSecondStartValue <= ONE_SEC_25MHZ_START;
  OneSecondEndValue <= ONE_SEC_25MHZ_END; 

  OneSecondCounter: counter
    generic map(
      COUNTER_WIDTH => ONE_SEC_25MHZ_WIDTH
    )
    port map(
      clock => InvertedSystemClock,
      reset => low,
      overflow => OneSecondClock,
      Min_Count => OneSecondStartValue,
      Max_Count => OneSecondEndValue,
      count_enable => high,
      count => OneSecondCounterOutput,
      input_count => OneSecondStartValue,
      load_enable => low
    );

  SystemClockStartValue <= SYS_CLOCK_START;
  SystemClockEndValue <= SYS_CLOCK_END;

  SystemClockCounter: counter
    generic map(
      COUNTER_WIDTH => SYS_CLOCK_COUNTER_WIDTH
    )
    port map(
      clock => clock_at_25175000_Hz,
      reset => low,
      overflow => systemClockOverflow,
      Min_Count => SystemClockStartValue,
      Max_Count => SystemClockEndValue,
      count_enable => high,
      count => SystemClockCounterOutput,
      input_count => SystemClockStartValue,
      load_enable => low
    );

  clocker: process(clock_at_25175000_Hz) is
  begin
    if rising_edge(clock_at_25175000_Hz) then
      if systemClockOverflow = '1' then
        SystemClockValue <= not SystemClockValue;
      end if;
    end if;
  end process clocker;


end structural;