-------------------------------------------------------------------------------- -- Chip.vhd -- top-level chip entity layout -- created: 1998 Oct 5, Sydney Tang -- -- 974 (84%), 4 EABs (8.1, Julian, noerck) -- 1090 (94%), 4 EABs (8.1, Gregorian, with error checking) -- 1141 (99%), 4 EABs (8.1, Gregorian, with error checking, new keydecoder) -- -- The Chip entity defines the I/O of the chip itself. Any inputs and outputs -- here correspond to actual pins that we use on the PLD. -- -- Internally, the chip contains the top-level VHDL entities and their -- interfaces to each other, as well as their interfaces to the chip's pins. -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.Constants_Package.all; use work.Time_Package.all; use work.Counter_Package.all; use work.Keypad_Package.all; use work.Control_Package.all; use work.LCD_Package.all; entity Chip is port( clock: in std_logic; -- 25 Mhz clock reset: in std_logic; state: out std_logic_vector(STATE_WIDTH-1 downto 0); diagnostics: out std_logic_vector(DIAGNOSTIC_WIDTH-1 downto 0); keypadX: out std_logic_vector(3 downto 0); keypadY: in std_logic_vector(3 downto 0); -- outgoing instructions to the LCD display LCD_DB: out std_logic_vector(LCD_DB_WIDTH-1 downto 0); LCD_RS: out std_logic; LCD_RW: out std_logic; LCD_E: out std_logic; LCD_ready: out std_logic; keyAvailable: out std_logic; LEDalarm: out std_logic; -- light LED during an alarm speaker: out std_logic -- speaker output for alarms ); end Chip; architecture structural of Chip is signal clk: std_logic; signal oneSecondClock: std_logic; signal rst: std_logic; signal keyData: std_logic_vector(KEYPAD_DATA_WIDTH-1 downto 0); signal keyDataAvailable: std_logic; signal keyAcknowledged: std_logic; signal currentState: std_logic_vector(STATE_WIDTH-1 downto 0); signal LCDcharacter: std_logic_vector(CHAR_WIDTH-1 downto 0); signal LCDinstruction: std_logic_vector(LCD_INSTRUCTION_WIDTH-1 downto 0); signal LCDready: std_logic; signal speaker_out: std_logic; --signal general_diagnostics: std_logic_vector(DIAGNOSTIC_WIDTH-1 downto 0); begin ---------------------------------------------------------------------- -- one-second clock SystemClock: ClockGenerator port map( clock => clock, SystemClock => clk, OneSecondClock => oneSecondClock ); ---------------------------------------------------------------------- -- low-level keypad driver KeyPadDecoder: keydecoder port map( clock => clk, --reset => rst, Ack => keyAcknowledged, keyData => keyData, keyDataAvailable => keyDataAvailable, -- input from keyboard col_output => KeypadX, row_input => KeypadY ); --rst <= keyData(3) and keyData(2) and keyData(1) and keyData(0); rst <= not reset; diagnostics <= keyData; KeyAvailable <= keyDataAvailable; ---------------------------------------------------------------------- -- LCD driver LCD_ready <= LCDready; LCDdriver: LCD port map( clock => clk, reset => rst, -- incoming instructions from Control --currentState => currentState, character => LCDcharacter, instruction => LCDinstruction, LCDready => LCDready, -- outgoing instructions to the LCD display DB => LCD_DB, RS => LCD_RS, RW => LCD_RW, E => LCD_E ); ---------------------------------------------------------------------- -- central control unit Controller: Control port map( -- basic input clock => clk, reset => rst, oneSecondClock => oneSecondClock, currentState => currentState, --diagnostics => general_diagnostics, -- input from Keypad driver keyData => keyData, keyDataAvailable => keyDataAvailable, keyAcknowledged => keyAcknowledged, LCDready => LCDready, -- instructions to LCD driver LCDcharacter => LCDcharacter, LCDinstruction => LCDinstruction, -- general output LEDalarm => LEDalarm, speaker => speaker_out ); speaker <= not speaker_out; state <= not currentState; --diagnostics <= general_diagnostics; ---------------------------------------------------------------------- end structural;