-- file "transmit.vhd"
--------------------------------------------------------------
-- controls the pulsing of the ultrasonic transmitter
-- to a certain frequency, has built-in clock divider which
-- was adapted from "VHDL Primer" by J. Bhasker, p. 295
-- written by Shaun Luong, Clifton Yeung, Jon Paul Kansky
-- and Patrick Asiedu-Ampem, University of Alberta
-- November 1998
------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity transmit is
	generic(divisor: positive:= 313);	-- change this to change frequency
										-- equal to "N" in Bhasker book
	port
	(
		reset, clock, enable: in std_logic;
		pulse: buffer std_logic
	);
end transmit;

architecture behavioural of transmit is
begin
	process(reset, clock)
		variable count: natural;
	begin
		if reset = '0' then				-- active low
			count := 0;
			pulse <= '0';
		elsif rising_edge(clock) then
			if enable = '1' then
				count := count + 1;
				if count = divisor then
					pulse <= not pulse;
					count := 0;
				end if;
			else
				count := 0;
				pulse <= '0';
			end if;
		end if;
	end process;
end behavioural;