-- file "timer.vhd"
-----------------------------------------------------------------------
-- counts the number of clock pulses between two triggers
-- written by Clifton Yeung, Shaun Luong, Jon Paul Kansky
-- and Patrick Asiedu-Ampem, University of Alberta
-- November 1998
-----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity timer is
	generic(counter_width: positive:= 19);
	port
	(
		clock, reset, sys_reset: in std_logic;
		latch_on, latch_off: in std_logic;
		output: out std_logic_vector(counter_width-1 downto 0)		
	);
end timer;

architecture counting of timer is

	signal stepper: std_logic_vector(counter_width-1 downto 0);

begin

	process(sys_reset, reset, clock)

		variable count: boolean;

	begin

		if sys_reset = '0' then
			output <= (others => '0');

		elsif reset = '1' then					-- active high
			count := false;
			stepper <= (others => '0');
			
		elsif rising_edge(clock) then
			if latch_on = '1' then			-- triggers are
				if latch_off = '0' then		-- active high
					count := true;
				else
					count := false;
				end if;
			elsif latch_off = '1' then
				count := false;
			end if;

			if count = true then
				stepper <= stepper + 1;
			elsif count = false then
				stepper <= stepper;
				if latch_off = '1' then
					output <= stepper;
				end if;
			end if;		
		end if;	

	end process;

end counting;