-- file "FPGA.vhd"
--------------------------------------------------------------------------
-- the top-level file for the FPGA chip for the 2-D Room Mapper
-- instantiates all the other component modules
-- written by Shaun Luong, Clifton Yeung, Jon Paul Kansky
-- and Patrick Asiedu-Ampem, University of Alberta
-- November 1998
----------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FPGA is
	generic
	(
		timer_width: positive:= 19;			-- # bits for timer output
		multiplier_width: positive:= 38;	-- # bits for distance output
		rotate_width: positive:= 6;			-- # bits for counter output
		rotate_num: positive:= 10			-- 10 phase changes = 10 degrees
											-- for stepper motor
	);
	port
	(
		clock, reset, start, move: in std_logic;	-- external board controls
		rx_pulse: in std_logic;						-- receiver pulse
		tx_pulse: buffer std_logic;					-- transmitter pulse
		motor_a, motor_b: buffer std_logic;			-- stepper motor output
		A1,B1,C1,D1,E1,G1,F1: out std_logic;		-- on-board 7-segment
		A2,B2,C2,D2,E2,G2,F2: out std_logic;		-- LED display
		red, green, blue: out std_logic;			-- VGA monitor color controls
		H_sync, V_sync: out std_logic				-- VGA monitor sync. controls
	);
end FPGA;

architecture structural of FPGA is

	-- component interconnect signals
	signal sys_clk, motor_clk: std_logic;
	signal pulse_tx, dist_reset: std_logic;
	signal timer_reset, latch_on, latch_off: std_logic;
	signal done_multiply, rotate_done, map_done: std_logic;
	signal motor_reset, start_rotate, rotate : std_logic;
	signal position: std_logic_vector(rotate_width-1 downto 0);
	signal pulses: std_logic_vector(timer_width-1 downto 0);
	signal length, VGA_dist, VGA_dummy: std_logic_vector(multiplier_width-1 downto 0);
	
-- component module declarations

	-- clock divider module
	component clk_div
		generic(N: positive);
		port
		(
			fast_clk, reset: in std_logic;
			slow_clk: buffer std_logic
		);
	end component;

	-- transmitter module
	component transmit
		generic(divisor: positive);
		port
		(
			reset, clock, enable: in std_logic;
			pulse: buffer std_logic
		);
	end component;

	-- pulse counter module
	component timer
		generic(counter_width: positive);
		port
		(
			clock, reset, sys_reset: in std_logic;
			latch_on, latch_off: in std_logic;
			output: out std_logic_vector(counter_width-1 downto 0)
		);
	end component;

	-- distance finder module
	component distance
		generic(distance_width, pulse_width: positive);
		port
		(
			clock, reset: in std_logic;
			pulse_count: in std_logic_vector(pulse_width-1 downto 0);
			distance: out std_logic_vector(distance_width-1 downto 0);
			done: out std_logic
		);
	end component;

	-- motor control module
	component rotater
		generic(pulse_num: positive);
		port
		(
			clock, reset: in std_logic;
			start: in std_logic;
			rot_enable: out std_logic;
			stop: out std_logic
		);
	end component;

	-- position module
	component motor2
		port
		(
			reset, clk, enable: in std_logic;
			outa, outb: buffer std_logic
		);
	end component;

	-- rotations counter module
	component bi_count
		generic(count_width,count_number,count_direction: positive);
		port
		(
			reset, count_enable: in std_logic;
			count: out std_logic_vector(count_width-1 downto 0);
			done: out std_logic
		);
	end component;

	-- LED display module
	component BCD
		port
		(
			A1,B1,C1,D1,E1,G1,F1 : OUT STD_LOGIC;
			A2,B2,C2,D2,E2,G2,F2 : OUT STD_LOGIC;
			INPUT : IN std_logic_vector (5 downto 0)
		);
	end component;

	-- VGA display module
	component monitor
		generic (N: positive);
	   	port
		(
			Clock, reset: in std_logic;
			Red,Green,Blue: out std_logic;
			Horiz_sync,Vert_sync: out std_logic;
			Distance_in: in std_logic_vector(N*3+7 downto 0);
			dummy_out: out std_logic_vector(N*3+7 downto 0)
		);
	end component;

	-- control module
	component control
	    port
		(
			clock, reset, start, move: in std_logic; 
			received_ultra,	done_distance: in std_logic;
			done_rotate, done_map: in std_logic;
			reset_timer, start_timer, stop_timer: out std_logic;
			send_ultra, reset_dist: out std_logic;
			reset_motor, rotate_10: out std_logic
		); 
	end component;

begin

-- instantiate the components

	-- system clock
	clk_sys: clk_div
		generic map(N => 1)
		port map
		(
			fast_clk => clock,
			reset => reset,
			slow_clk => sys_clk
		);

	-- motor clock
	clk_motor: clk_div
		generic map(N => 2500000)
		port map
		(
			fast_clk => clock,
			reset => reset,
			slow_clk => motor_clk
		);

	-- transmitter control
	tx_control: transmit
		generic map(divisor => 313)
		port map
		(
			reset => reset,
			clock => clock,
			enable => pulse_tx,
			pulse => tx_pulse
		);
	
	-- pulse counter
	pulse_count: timer
		generic map(counter_width => timer_width)
		port map
		(
			clock => sys_clk,
			reset => timer_reset,
			sys_reset => reset,
			latch_on => latch_on,
			latch_off => latch_off,
			output => pulses	
		);

	-- distance finder
	convert: distance
		generic map
		(
			distance_width => multiplier_width,
			pulse_width => timer_width
		)
		port map
		(
			clock => sys_clk,
			reset => dist_reset,
			pulse_count => pulses,
			distance => length,
			done => done_multiply
		);

	-- motor control
	motor_control: rotater
		generic map(pulse_num => rotate_num)
		port map
		(
			clock => motor_clk,
			reset => motor_reset,
			start => start_rotate,
			rot_enable => rotate,
			stop => rotate_done
		);

	-- position module
	positioner: motor2
		port map
		(
			reset => motor_reset,
			clk => motor_clk,
			enable => rotate,
			outa => motor_a,
			outb => motor_b
		);
	
	-- rotation counter
	rotate_counter: bi_count
		generic map
		(
			count_width => rotate_width,
			count_number => multiplier_width,
			count_direction => 1
		)
		port map
		(
			reset => reset,
			count_enable => rotate_done,
			count => position,
			done => map_done
		);

	-- LED display
	LED_display: BCD
		port map
		(
			A1 => A1,
			B1 => B1,
			C1 => C1,
			D1 => D1,
			E1 => E1,
			G1 => G1,
			F1 => F1,
			A2 => A2,
			B2 => B2,
			C2 => C2,
			D2 => D2,
			E2 => E2,
			G2 => G2,
			F2 => F2,
			INPUT => position
		);
	
	-- VGA display
	VGA_display: monitor
		generic map(N => 10)
	   	port map
		(
			Clock => clock,
			reset => reset,
			Red => red,
			Green => green,
			Blue => blue,
			Horiz_sync => H_sync,
			Vert_sync => V_sync,
			Distance_in => length,
			dummy_out => VGA_dummy
		 );

	-- control module
	controller: control
		port map
		(
			clock => sys_clk,
			reset => reset,
			start => start,
			move => move,
			received_ultra => rx_pulse,
			done_distance => done_multiply,
			done_rotate => rotate_done,
			done_map => map_done,
			reset_timer => timer_reset,
			start_timer => latch_on,
			stop_timer => latch_off,
			send_ultra => pulse_tx,
			reset_dist => dist_reset,
			reset_motor => motor_reset,
			rotate_10 => start_rotate
		);
				
end structural;