Memory Interface VHDL Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;

entity ramm is

port(    write_data_A,
        write_data_B,
        write_data_C,
        write_data_D : in std_logic_vector(7 downto 0);
        address_A,
        address_B,
        address_C,
        address_D : in std_logic_vector(7 downto 0);
        mem_request_A,
        mem_request_B,
        mem_request_C,
        mem_request_D : in std_logic;
        we_A, we_B, we_C, we_D, clock     : in std_logic;

        read_data_A,
        read_data_B,
        read_data_C,
        read_data_D : out std_logic_vector(7 downto 0);
        mem_ready_A,
        mem_ready_B,
        mem_ready_C,
        mem_ready_D : out std_logic);
end ramm;


architecture behavioural of ramm is


constant DATA_WIDTH : positive := 8;
constant ADDR_WIDTH : positive := 8;

signal address_in : std_logic_vector(7 downto 0);
signal read_data, write_data : std_logic_vector(7 downto 0);
signal mem_status : std_logic_vector(3 downto 0);
signal we, busy, invclock : std_logic;

begin

memory_array: lpm_ram_dq
    GENERIC MAP (    lpm_widthad => ADDR_WIDTH,
            lpm_width => DATA_WIDTH,
                    lpm_file => "init.mif")

    port map (    data => write_data, address => address_in,
                we => we, q => read_data,
                inclock => clock, outclock => invclock);

invclock <= not clock;
busy <= mem_request_D or mem_request_C or mem_request_B or mem_request_A;

mem_ready_A <= mem_status(0);
mem_ready_B <= mem_status(1);
mem_ready_C <= mem_status(2);
mem_ready_D <= mem_status(3);

choose_op : process
begin
wait until clock'event and clock = '0';
if busy='1' then
    if mem_request_D = '1' then
        address_in <= address_D;
        read_data_D <= read_data;
        write_data <= write_data_D;
        we <= we_D;
        mem_status <= "1000";
    elsif mem_request_C = '1' then
        address_in <= address_C;
        read_data_C <= read_data;
        write_data <= write_data_C;
        we <= we_C;
        mem_status <= "0100";
    elsif mem_request_B = '1' then
        address_in <= address_B;
        read_data_B <= read_data;
        write_data <= write_data_B;
        we <= we_B;
        mem_status <= "0010";
    elsif mem_request_A = '1' then
        address_in <= address_A;
        read_data_A <= read_data;
        write_data <= write_data_A;
        we <= we_A;
        mem_status <= "0001";
    else
        we <= '0';
        mem_status <= "0000";
    end if;
else
    we <= '0';
    mem_status <= "0000";
end if;
end process choose_op;

end behavioural;