------------------------------------------------------------------------

-- File: state_machine.vhd

--

-- Group: Korrey Scott 237118

-- Milton Mah 341428

-- Mike Holden 346386

--

-- Course: EE 552

-- Project: ASM

-- Instructor: Dr. Duncan Elliott

-- Completed: Mar. 27, 1998

------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

------------------------------------------------------------------------

-- Entity: state_machine

--

-- Inputs: select_button: signal provided by the push_to_change_state

-- module, representing a button push

-- reset: connected to the master reset, resets to inital

-- clock state

-- minutes: number of minutes provided by clockchip

--

-- hours: number of hours provided by clockchip

--

-- km_per_litre: the mileage of the automobile provided by mileage

--

-- velocity: the velocity of the automobile provided by speed

--

-- Outputs: state_vector: bit vector representing the state of the system

-- display

-- data1: bit vector holding the data of the present state

--

-- data2: only used in the clock state to hold the number of hours

------------------------------------------------------------------------

entity state_machine is

port (select_button,reset: in std_logic;

minutes: in integer range 0 to 59;

hours: in integer range 0 to 12;

km_per_litre: in integer range 0 to 127;

velocity : in integer range 0 to 127;

state_vector : out std_logic_vector ( 2 downto 0);

data1: out std_logic_vector ( 7 downto 0); -- transmits all

-- data ( or hours if clock state)

data2: out std_logic_vector ( 3 downto 0) -- only used to

-- transmit hours

);

end state_machine;

------------------------------------------------------------------------

-- Architecture: behaviour of state_machine

--

-- Description: The purpose of this module is to change the state of the

-- system on a high select_button signal, and, to put the

-- data of the given state on the data1 and data2 output lines

------------------------------------------------------------------------

architecture behaviour of state_machine is

type state_type is (speed,direction,mileage,clock);

signal state, next_state : state_type;

begin

state_select :process(select_button,reset)

begin

if reset = '1' then

state <= clock;

elsif rising_edge(select_button) then

case state is

when clock =>

state <= mileage;

when mileage =>

state <= speed;

when speed =>

state <= direction;

when direction =>

state <= clock;

end case;

end if;

end process state_select;

state_display :process(hours,minutes,km_per_litre,velocity)

variable temp_vector : std_logic_vector(7 downto 0);

variable minute_vector : std_logic_vector(7 downto 0);

variable hour_vector : std_logic_vector(7 downto 0);

begin

case state is

when clock =>

-- convert minutes and hours

hour_vector := conv_std_logic_vector(hours,8);

data2 <= hour_vector;

minute_vector := conv_std_logic_vector(minutes,4);

data1 <= minute_vector;

state_vector <= "001";

when mileage =>

temp_vector := conv_std_logic_vector(km_per_litre,8);

data1 <= temp_vector;

state_vector <= "011";

when speed =>

temp_vector := conv_std_logic_vector(velocity,8);

data1 <= temp_vector;

state_vector <= "111";

when direction =>

state_vector <= "101";

end case;

end process state_display;

end behaviour;