------------------------------------------------------------------------

-- File: push_to_change_state.vhd

--

-- Group: Korrey Scott 237118

-- Milton Mah 341428

-- Mike Holden 346386

--

-- Course: EE 552

-- Project: ASM

-- Instructor: Dr. Duncan Elliott

-- Completed: Apr. 3, 1998

------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

------------------------------------------------------------------------

-- Entity: push_to_change_state

--

-- Inputs: state_button: external push button used to change the system state

--

-- clkpulse: externally generated pulse at 1kHz

--

-- reset: master reset of the system

--

-- Outputs: change_state: a signal sent to state_machine.vhd that is set high

-- for one clkpulse

------------------------------------------------------------------------

entity push_to_change_state is

port (state_button, clkpulse, reset : in std_logic;

change_state : buffer std_logic);

end push_to_change_state;

------------------------------------------------------------------------

-- Architecture: behaviour of push_to_change_state

--

-- Description: This architecture was taken from lab #5 solutions by Dr. Elliott.

-- Only the names of the signals have been changed.

-- The purpose of this module is to detect a button push and

-- set its associated signal high for a duration of one clkpulse.

------------------------------------------------------------------------

architecture behaviour of push_to_change_state is

-- latched but not synchronized

signal change_state_latched, change_state_latched2 : std_logic;

begin

--SR latch built with AND and OR gates

change_state_latched2 <= change_state_latched or state_button;

change_state_latched <= change_state_latched2 and (not reset and state_button);

--this synchronizer (D-flip-flop) reduces the probablitlity of

--the asynchronous push button causing metastability

d_flipflop : process(clkpulse)

begin

if rising_edge(clkpulse) then

change_state <= change_state_latched;

end if;

end process d_flipflop;

end behaviour;