------------------------------------------------------------------------

-- File: clockchip.vhd

--

-- Group: Korrey Scott 237118

-- Milton Mah 341428

-- Mike Holden 346386

--

-- Course: EE 552

-- Project: ASM

-- Instructor: Dr. Duncan Elliott

-- Completed: Mar. 27, 1998

------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

------------------------------------------------------------------------

-- Entity: clockchip

--

-- Inputs: reset: connected to the master reset.

--

-- clkpulse: externally generated pulse of 1kHz.

--

-- hour_button: external push button to increment the hours

--

-- minute_button: external push button to increment the minutes

--

-- Outputs hour: the value of the hours of the sytem clock

--

-- minutes: the value of the minutes of the system clock

--

-- seconds_pulse: a 1 Hertz pulse generated by clock.vhd

------------------------------------------------------------------------

entity clockchip is

port (

reset, clkpulse, hour_button, minute_button: in std_logic;

hour : out integer range 0 to 12;

minute : out integer range 0 to 59;

seconds_pulse : out std_logic

);

end clockchip;

------------------------------------------------------------------------

-- Architecture: behaviour of clockchip

--

-- Description: The purpose of this module is to bring together the

-- push_to_set and clock modules

------------------------------------------------------------------------

architecture behaviour of clockchip is

signal set_hour_A : std_logic;

signal set_minute_A : std_logic;

component push_to_set

port (

hour_button : in std_logic;

minute_button : in std_logic;

clkpulse : in std_logic;

reset : in std_logic;

set_hour : buffer std_logic;

set_minute : buffer std_logic

);

end component;

component clock

generic (puls_per_sec : Natural := 10);

port (

reset : in std_logic;

clkpulse : in std_logic;

set_hour : in std_logic;

set_minute : in std_logic;

hour : out integer range 0 to 12;

minute : out integer range 0 to 59;

seconds_pulse : out std_logic

);

end component;

begin

chipclockmatch: clock port map(

reset => reset,

clkpulse => clkpulse,

set_hour => set_hour_A,

set_minute => set_minute_A,

hour => hour,

minute => minute,

seconds_pulse => seconds_pulse

);

chipclockset: push_to_set port map(

hour_button => hour_button,

minute_button => minute_button,

clkpulse => clkpulse,

reset => reset,

set_hour => set_hour_A,

set_minute => set_minute_A

);

end behaviour;