------------------------------------------------------------------------
-- File: Clock.vhd
--
-- Group: Korrey Scott 237118
-- Milton Mah 341428
-- Mike Holden 346386
--
-- Course: EE 552
-- Project: ASM
-- Instructor: Dr. Duncan Elliott
-- Completed: Feb. 21, 1998
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
------------------------------------------------------------------------
-- Entity: clock
--
-- Inputs: reset: connected to the master reset. Resets the clock
-- module to initial state. Time set to 1:00
-- clkpulse: external generated pulse used to determine time.
--
-- Outputs: hour: contains the hour (1 through 12).
-- minute: contains the minutes (0 through 59).
-- big_counter: increments each time a clkpulse is received. Used
-- for timing in other modules.
------------------------------------------------------------------------
entity clock is
generic (puls_per_sec : Natural := 1000);
port (
reset : in std_logic;
clkpulse : in std_logic;
set_hour : in std_logic;
set_minute : in std_logic;
hour : out integer range 0 to 12;
minute : out integer range 0 to 59;
seconds_pulse: out std_logic
);
end clock;
------------------------------------------------------------------------
-- Architecture: behaviour of clock
--
-- Description: The purpose of this module is maintain an accurate 12
-- hour clock.
------------------------------------------------------------------------
architecture behaviour of clock is
begin
timer :process(clkpulse,reset)
variable sec_counter : integer range 0 to 15;
variable second : integer range 0 to 59;
variable hour_bak : integer range 0 to 12 := 1;
variable min_bak : integer range 0 to 59 := 0;
variable last_hour_sig : std_logic := '0';
variable last_min_sig : std_logic := '0';
begin
wait until rising_edge(clkpulse);
if reset = '1' then
sec_counter :=0;
second :=0;
hour_bak := 1;
min_bak := 0;
else
seconds_pulse <= '0';
sec_counter := (sec_counter + 1);
if sec_counter >= puls_per_sec then
if second = 59 then
second := 0;
if min_bak = 59 then
min_bak :=0;
if hour_bak = 12 then
hour_bak := 1;
else
hour_bak := (hour_bak + 1);
end if;
else
min_bak := (min_bak + 1);
end if;
else
second := second + 1;
end if;
seconds_pulse <= '1';
sec_counter := 0;
end if;
hour <= hour_bak;
minute <= min_bak;
if set_hour = '1' then
if set_hour /= last_hour_sig then
if hour_bak = 12 then
hour_bak := 1;
else
hour_bak := hour_bak + 1;
end if;
end if;
end if;
last_hour_sig := set_hour;
if set_minute = '1' then
if set_minute /= last_min_sig then
if min_bak = 59 then
min_bak := 0;
else
min_bak := min_bak + 1;
end if;
end if;
end if;
last_min_sig := set_minute;
end if;
end process timer;
end behaviour;