ABSTRACT: *

IC DATA SHEET: *

CHIP OVERVIEW: *

DESIGN DETAIL: *

DESIGN VERIFICATION: *

IC TESTING: *

PROBLEMS ENCOUNTERED & SOLUTIONS *

CONCLUSION: *

References: *

The project that we chose to implement on the Actel Field Programmable Gate Array (FPGA) for our EE 552 project was that of a digital Theremin.

It consisted of four oscillators, two of which controlled pitch, and the remaining two controlled the volume. Two beat frequencies resulted from combining the outputs of each pair of oscillators. A frequency detector was utilized in the volume control circuit. It determined the beat frequency, which in turn determined the pulse width modulated signal that resulted and controlled the volume.

We designed the Theremin using VHDL and all the Actel resources. The first simulation was performed using QuickSim and was successful, though after Actmapping the code some problems arose in the back-annotated simulation.

In order for us to get the Theremin working we followed some advice given to use by Dr. Elliott. Simplify your design. So, we simplified our design, all we wanted at that point, was to get some sort of output. Maybe not!

Actel FPGA: Fam:Act1

Modules Used: 388 before optimizing, 371 after optimization

Delay of the Critical Path: 194.10 ns, so sys_clock must be < 1/194.10 ns

Refer to Pin Assignment Schematic

The Actel FPGA will interact with external components to form a digital Theremin. The chip will have a variable frequency input signal, controlled by a resistor and a capacitor, and will compare it with a fixed frequency signal. Thus, a beat frequency is generated. This beat frequency will then be fed through an ‘AND’ gate and a D-Flip Flop. The output is controlled using an external switch that is fed to the selector of a mux. With the switch, the player can select and output wave of either a pulse width modulated triangle wave or a rectangular wave. The output wave from the chip will be fed through a Low Pass Filter and then to a pair of amplified PC speakers. The chip’s top-down hierarchy is as follow: Pitch and volume mixer, pitch control, which consists of two oscillators, volume control, which consists of a frequency detector, and finally, two oscillators. We will describe each component of the circuit starting at the lowest level of the design, the two oscillators. These details can be found in the following section, Design Details.

The oscillators consist of three inverters connected in series. The inverters act to flatten the incoming wave to produce a string of ones and zeroes. The incoming wave is produced by an input resistance and a capacitance, where the capacitance is controlled by the distance of the theremin player’s hand from the antenna. The frequency of the oscillators is controlled by an output capacitance and a resistance. The signal into the chip is taken from the output of the third inverter, which is buffered to the output resistance. Refer to "Schematics" in the Appendix.

The frequency detector was written using VHDL and was composed of four major processes, slo_clk (slow clock), counts, volume_assign, and pulse_width. First off, slo_clock is a counter that creates the time over which a frequency is counted. It uses the system clock, know to be four megahertz, and counts up to 0.25 seconds. After 0.25 seconds, the present value of slo_clock is inverted.

The process ‘counts’ utilizes the component ‘counter’. The component ‘counter’ is enabled whenever the process ‘counts’ realizes a rising edge in the beat frequency. Also, there must be no change in the slo_clock. When there is a change in the slo_clock, the value in ‘counter’ is loaded into the signal ‘freq’ (frequency) and then the counter is reset.

The volume_assign process assigns a value to the volume level, which is dependent upon the signal ‘freq’ which resulted from the process ‘counts’. There is ten levels of volume hence there are ten different widths of volume output. If reset = 0 then the default volume level is 10.

The process pulse_width takes the width value from the volume_assign process. It uses this value as the limit to which the width counter (w_count) can go up to. This results in a pulse width modulated signal of the desired volume level.

The pitch control mixes the two input frequencies depending upon the position of the p_switch (pitch switch). If p_switch is equal to 0 then the signals are ‘anded’ together if not, the frequencies are mixed using a D-Flip Flop where frequency one is the clock input and frequency two is the D input. The resulting signal is the pitch output (beat frequency).

The volume control acts similar to that of the pitch control except that the beat frequency is further analyzed through the frequency detector program. The resulting output is a pulse width modualted wave out of the frequency detector program.

The output of the volume and pitch mixer is dependent upon a switch as well. If the switch is high, the output is tri-state otherwise the output is volume and pitch signals ‘anded’ together. The tri-state works as follows, when both signals are high, the result is high as well, if the signals are not equal, the result is ‘Z’. If both signals are low the result is ‘0’.

The initial VHDL code was simulated using DESIGN ARCHITECT and QUICKSIM, it appeared to work without errors. Then the current code was synthesized using ACTMAP into a code that would be used for the actual chip. The code generated by the ACTEL designer methods did not simulate correctly, so, many alterations to the initial code had to be made.

We did not test the actual IC, as we did not actually burn a chip. Our original design failed to simulate properly when back-annotated, and our simplified design would not compile properly. Much time was spent on the simplified design, there were no errors to be seen, but it still would not compile. Reasoning might be that a small but significant setting was when Actmapping.

Various problems arose in synthesis of the VHDL code. First, Actmap found it difficult to understand some of the VHDL code. Actmap had problems with "complicated" if loops, these loops had to be revised to suit Actmap. Assigning signals to other signals did not work well either, dummy signals were used to avoid this problem. In Actel Designer having two types of "’events" synthesized as having two system clocks which was not allowed. In our program we used a beat frequency event to enable a counter. This along with the system clock was not good. To avoid this we made processes that would assign a state to a signal depending on whether there was a change in another signal. (see processes ‘trig_slow and old_slow’ of program freq_detect.vhd in Apendix. There were in general, many glitches that we came across that were fixed but are now forgotten.

Most problems were solved by synthesizing each sub-program into a chip and simulating that with various testbenches. One example is the counter which did not work initially, we performed back-annotated simulation on it separately until it worked. The waveforms that resulted are also in the Appendix. Though this method of debugging was successful it took a very long time because you had to go through so many processes. In the end, we ran out of time to debug the rest of the program.

Other problems encountered were, general lab problems, one weekend the system was down, my account reached its quota, and I ended up wasting much time trying to make room, (thanks Dr. Elliott for upping my quota.)

Our last attempt to get something working was the Chipper attempt. It was a simple design, but for some reason it would complete a LAYOUT in Actel Designer, it always cut out at 88% of standard Layout. This problem was never solved, though we were told it was most likely something in our top-level file. We could not identify any problems so this attempt was discarded.

One definite solution to all our problems was to have started earlier. Despite the warnings given, we did not start soon enough. Though this was also difficult because much time was spent, and needed to get oriented with the Actel Programs.

Designing of the Theremin has provided us with many experiences, good and bad. We have learned the start to finish procedures of designing a project.

We started by choosing a project, the Theremin, and then spent time researching the basic ideas behind the Theremin. Easy? I don’t think so! Next, we sat down designed the Theremin using Design Architect. Oops, we didn’t use any VHDL, so we revamped our design to include some VHDL which, in turn, led to programming the entire design in VHDL. This worked when originally simulated but when it came to the back-annotated design, that was another story. The back-annotated simulation failed miserably. Back to the drawing board! To make the Theremin work, in the time left, we were going to have to simplify our design. We cut out the volume control circuit and modified the pitch circuit. We rewrote the code, and kept getting the same error of "88%". Time ran out, and we did not complete the project.

All in all, this project and course have provided us with valuable experiences in FPGA design. Many considerations have to be made when designing for the FPGA. The most prominent aspect that we originally failed to consider was making sure that our design could be implemented on the chip. There were many constraints to consider: number of modules, could the VHDL code be implemented on the chip, the number of available input/output ports, etc.

Design can be difficult, or it can be easy, it depends how you approach your project.

We found that the time factor played the largest roll in the completion of this project. If only a few messages could be relayed to future students of this course, they would include: start planning your project before the beginning of the course. Start early, plan ahead, partition your project into small chunks, don’t try to design it all at once, know the lab hours well, and drink lots and lots of Coca-Cola or Coffee, depending on your preference.

• Actel FPGA Data Book and Design Guide, 1996, Actel Corporation
• VHDL Made Easy, ????, Pellerin & Taylor

• www.mark-itt.ru/~db/termen.htm
• www.techweb.com/se/directlink.cgi?EET19970728S0008
• www.physics.gla.ac.uk/~kskeldon/PubSci/exhibits/E9/
• http://www.nashville.net/~theremin/EPEArticle.html

• www.ualberta.ca/~dyee/theremin/theremin.htm