EE 552 PROJECT: DIGITAL SYNTHESIZED RADIO TRANSMITTER
Anco Snip, snip@ee.ualberta.ca
John Forcadas,
forcadas@ee.ualberta.ca
ABSTRACT
This report outlines the design, fabrication and testing of a digitally synthesized radio transmitter that could be used in conjunction with a series of detection instruments for wireless transmission of a distress signal resulting from fire or smoke detection. The radio transmitter was designed to be tunable so that the desired carrier frequency could be dynamically adjusted up or down in the frequency range of 1 - 4 MHZ with the resulting frequency displayed on a two-digit LED. The device contained a digital phase-locked loop for frequency synthesis with additional analog and testing components and was implemented on an Actel FPGA. The transmitter was designed to accept an enable signal from two separate detection devices connected to it. When a device was enabled, the transmitter emitted a 4 bit code preceded by two framing bits corresponding to which of the two devices had been triggered, or it transmitted both codes if both had been enabled at the same time or separately. This code was transmitted at a rate of 1 kHz and was modulated with the carrier frequency using on-off keying (OOK). The final signal was routed through 5 output pins on the FPGA and passed through an analog filter before passing through an AM antenna. Our transmitter design also contained extra output pins for testing purposes of each functional block and for implementing an external VCO if the internal one did not function properly.
CONTENTS
1 Project Overview
2 IC Data Sheet
3 Design Details
3.1 PLL Frequency Synthesizer Design.....................................
3.1.1 Phase Detector.......................................................
3.1.2 Voltage Controlled Oscillator.................................
3.1.3 Low Pass Filter.......................................................
3.1.4 Divide-by-N Counter...............................................
3.2 Other Components
3.2.1 Crystal Oscillator................................................
3.2.2 Prescalars.............................................................
3.2.3 LED Display.........................................................
3.2.4 Output Filter..........................................................
3.3 Modulator
4 Design Verification
4.1 Simulation
5 Testing
5.1 VCO Testing......................................................
5.2 Complete System Test Results.................................
6 Conclusions
7 References
8 Appendix
8.1 Other VHDL code........................................................
8.2 Other Schematics........................................................
8.3 LED Display Karnaugh Maps.....................................
1.0 Introduction
The motivation for this design is that for safety and security considerations, a smoke detection device that could transmit a wireless warning signal would obviate the need for someone in the vicinity to hear and would not need the use of transmission wires that could be damaged in the event of a sudden explosion.
1.1 Project Description
For the transmission circuit, two separate smoke alarms which could be located in separate rooms or process tanks were each connected to an input pin of the FPGA. When an alarm is triggered, the detector will enable the radio transmitter to transmit a four bit identification code that uniquely identifies that particular detector so the receiver can gauge the location and severity of the blaze instantly. The four bit codes were 1111 for detector_1 and 1101 for detector_2. Two 00 framing bits were used to determine the start of the transmission.
The carrier frequency for transmission was designed to be tunable in a range from 1 to 4 MHZ in increments of 100 KHz. One switch incremented the counter up 100 kHz, the other down 100 kHz. An asynchronous reset button resets the carrier frequency to 2.5 MHZ. The transmission frequency was designed to be displayed on a two-digit LED representing 100s of KHz.
For modulation of the carrier frequency, a form of on-off keying was utilized at a data rate of 1 kHz. Essentially, it is a simple AM mode whereby a zero modulated with the carrier frequency resulted in a zero at the output and a one resulted in a series of ones.
An analog crystal oscillator at 8 MHZ and scaled down to 100 kHz was used to set the reference frequency for the timer circuit and a digital voltage controlled oscillator (VCO) was used to set the carrier frequency. A divide by N counter, whereby N can be manually adjusted up or down was designed to delay the VCO frequency so that the carrier frequency can be tuned and displayed. A phase-detector circuit compares the reference clock frequency with that of the divided VCO frequency and adjusts the voltage accordingly. If the VCO frequency lags that of the clock, it will increase the voltage delivered to the VCO thereby increasing the carrier frequency but equalizing the frequencies at the phase-detector. The divide by N circuit was implemented in VHDL with a Finite State Machine with three inputs: up, down and reset.
DIGITAL SYNTHESIZED RADIO TRANSMITTER
From the block diagram we see that the design can be broken up into seven separate entities.
1.2 Functional Component Blocks
From the block diagram we see that the design can be broken up into seven separate entities.
1) Clock Signal Generator - A crystal oscillator operating at a reference frequency of 8 MHZ was used as system clock for all circuit timing and as the reference input for the phase comparator. It was designed using the circuit described on the Actel data sheet for crystal oscillators using a 10 Mohm and 1 kohm resistor and two 18 pF capacitors. It required one input pin and one output pin on the Actel FPGA.
2) Clock Prescaler - Enabled to reduce the clock frequency for generation of lower
frequencies. It was implemented in VHDL using simple counter circuits. A divide by eight and a divide by ten counter in series were enabled and used to reduce the clock frequency to 100 kHz to be used as the reference input into the phase comparator of the phase locked loop (PLL). This signal was further reduced by two subsequent divide by ten counters to be used as the data rate for the modulator at 1 kHz.
3) Phase Detector - The phase detector compares the phase of the reference clock pulse
(100 kHz) with that of the divided VCO frequency and emits a pulse of variable length to the VCO to equalize the two signal frequencies. The phase detector was designed using schematic capture based on a design in the Actel data book. Involves a J-K flip-flop and combinational logic.
4) VCO - The voltage controlled oscillator was implemented according to the Actel design guide. It was implemented in VHDL with two output pins and one input pin and external components. The output frequency of the VCO is determined by the voltage at its input which is altered by the phase detector pulses. An additional input allowed an external IC VCO to be used to test the circuit and for use in the case that the internal one did not function correctly.
5) Divide by N counter - This is a variable counter controlled by a FSM implemented in VHDL. One input pin increased the carrier frequency by 100 kHz to a maximum of 4 MHZ, and the other reduced the carrier frequency by 100 kHz to a minimum of 1 MHz. A reset button set the carrier frequency back to 2.5 MHZ.
6) Modulator - The modulator was implemented using VHDL. When detector_1 was enabled the modulator emitted a 001111 signal at a data rate of 1 kHz and a 001101 when detector_2 was enabled and it emitted 001111001101 ... when both were enabled. This signal continued until reset even if the input signals became disabled. This 1 kHz signal was modulated with the carrier frequency at 1 - 4 MHZ to form an AM OOK signal that could be tested using an AM radio.
7) External Filter and Antenna - External analog components to broadcast the generated signal. The filter was comprised of a capacitor, resistor and inductor with five FPGA outputs tied to its input and a 50 ohm AM antenna connected to the output.
2.0 IC Data Sheet
FPGA - Actel 44 PLCC
- 34 I/O pins, 261 modules
Component Block Pin # Name FPGA Function
Divide by N Counter Reset 42 Reset system, set carrier frequency to 2.5 MHZ.
Countup 41 Increase carrier frequency 100 kHz.
Countdown 40 Decrease carrier frequency 100 kHz.
LED Display LED0-13 17, 15, 13, Displays one segment of LED.
12, 11, 9, 8
7, 6, 5, 4, 2,
44, 1 RF filter Loopfilter 20 Output of phase detector, to VCO.
Testdiv 22 Test output of divide by N counter.
Crystal Oscillator Osc1 19 Input from crystal oscillator.
Osc2 18 Output from FPGA to oscillator.
Modulator Ant0-4 29, 33, 30 Output of modulator to filter and
37, 38 AM antenna.
Detector_1 39 Detector_1 enable.
Detector_2 36 Detector_2 enable.
VCO Select_VCO 27 Choose either internal or external VCO.
VCO1 24 Input from internal VCO external analog circuitry.
VCO2,3 23, 26 Output form FPGA to internal VCO external analog circuitry.
IcVco 28 Input to FPGA from external IC VCO.
TestVco 31 Test output signal from either internal or external VCO for correct function.
Other Mode 34
Vcc 3, 14, 16,
25, 35
Gnd 10, 21 32, 43
Additional Components
1 VCO integrated circuit with filter for testing purposes and in the event of failure of the FPGA implemented digital VCO.
2 one digit LED displays.
1 Eight MHZ crystal oscillator.
1 RF filter and AM antenna.
Several push buttons.
10 - 15 resistors.
5 capacitors for external filters, clock circuit and internal VCO.
1 radio and oscilloscope for signal detection and testing.
1 DC power supply.
3 DESIGN DETAILS
3.1 PLL Frequency Synthesizer
The block diagram of a Phase-Locked Loop is shown below.
There are four different types of Phase-Locked Loops. They are:
1) The Linear PLL (LPLL). In this topology, all parts are implemented using analog
components.
2) The Digital PLL (DPLL). In this topology, the phase detector is digital, but the
VCO and the filter are analog.
3) The All Digital PLL (ADPLL). In this topology, all parts are implemented using
digital components.
4) The Software PLL (SPLL). The PLL is implemented using a microcontroller or
a digital signal processor. The PLL algorithms are implemented using software.
For our project, we chose to implement the frequency synthesizer using the DPLL. We could also have used an ADPLL, however, this would have required an additional high frequency clock (i.e., at least N*F_ref). Nevertheless, the ADPLL eliminates the need for an analog loop filter and an analog VCO.
3.1.1 Phase Detector
In commercially available PLL integrated circuits, three different phase detectors are commonly used. A brief overview of their operation will explain why we chose to use the edge triggered JK-Flip flop for our design. They are:
1) Exclusive OR gate. The duty cycle of the output of this gate is directly proportional to the phase difference between the two input signals. If the two signals are in phase, the output is zero. When the input frequency is maximum, the VCO input must be maximum and hence the phase detector inputs must be 180
º out of phase. For good operation, both input signals must have a duty cycle of 50 % (i.e. they must be symmetrical).
2) Edge triggered JK-Flip Flop. This phase detector works by detecting the rising edges of the input signals as shown in the timing diagram below.
Also in this case, the duty cycle of the phase detector output is proportional the the phase error of the input signals. In our design J is the reference frequency and K is the output of the frequency divider. From the above timing diagram it can be seen that the VCO is generating a lower frequency than required. Hence the duty cycle of the output increases. The output Q charges the low pass filter until the LPF output equals Vcc. This will correspond to a VCO output of maximum frequency.
The operation of this phase detector differs from the operation of the exclusive OR gate. When the two input signals have 180
º phase error, the duty cycle of the output will be 50 %. This condition corresponds to the center frequency. Hence, this phase detector can detect a phase difference from 0 º to 360 º. (The exclusive OR gate can detect a phase error in the range from 0 to 180º). The main advantage of this detector over the exclusive OR gate is that the two input signals do not have to have a 50 % duty cycle and they can be asymmetrical. This in fact is the reason why we used this phase detector. It is difficult, if not impossible, to design a synthesizable programmable divider in VHDL which has a constant duty cycle of 50 %. The disadvantage of this type of phase detector is its behavior when the phase error is close to zero, i.e. there is a rising edge on both inputs almost simultaneously.
3) Phase-Frequency Detector.
This is the best phase detector for most applications that do not involve a lot of noise. A circuit diagram is shown below.
The AND gate prevents the state where UP and DOWN are both 1 because the Cd ("Clear direct") inputs will go high forcing the Q’s to 0. Hence this is a tri-stateable device. The state transitions occur on rising edges at the D inputs. The MOSFET’s are required for generating the high-impedance state corresponding to UP and DOWN both 0. The main advantage of this phase detector is that its pull-in range is infinite, i.e. no it will always lock onto the input frequency regardless of the size of the frequency step applied to the input. However, we did not use it in our design since it requires the two external MOSFETs and also because we did not require an infinite pull-in range. We had to make sure that the JK-flip flop would have a Lock range of at least 100 kHz since everytime the frequency divider count is incremented or decremented, a frequency step of 100 kHz will be applied to the input of the phase detector. The JK- flip flop was able to meet this specification.
The VHDL description of the JK-flip flop is very simple:
entity pd is
port(J: in std_logic; K: in std_logic; Q: out std_logic);
end pd;
architecture JKff of pd is
begin
process(J, K)
begin
if rising_edge(J) then
Q <= ‘1’;
elsif rising_edge(K) then
Q <=’0’;
end if;
end process;
end JKff;
However, this will not synthesize because of the concurrent rising_edge statements.
We implemented the JK flip flop using schematics as shown on the next page. Also note that we added an asynchronous clear for simulation purposes. The schematics were converted to structural VHDL via the path: Schematics => mgc2edn => edn2vhdl => VHDL.
3.1.2 Voltage Controlled Oscillator
As described in the project overview the Voltage Controlled Oscillator (VCO) is required to generate a frequency of 1 MHz to 4 MHz. Our approach was to try a VCO design using the FPGA and discrete components. In case this approach did not work we included a selectvco pin and an icvco pin on the FPGA in order to be able to use an IC. The behavior of the VCO can be described by the following equation:
w_out = w_o + K0 * (Vin - Vcc/2) (1)
where:
w_out = the frequency of the VCO outputw_o =
the center frequency of the VCO outputK0
= the VCO gain factorVin = the voltage at the VCO input
Hence,
w_out = w_o when Vin = Vcc/2 as required at the center frequency.The discrete design we tried is shown below.
The MVAM 108 is a tuning diode with a high capacitance ratio (minimum is 15). The capacitance ranges from 440 pF to 560 pF. Nevertheless, when we tested this circuit the frequency of the output was almost constant at 32.1 kHz. There was a 0.3 V voltage drop across the 1.8 M
W resistor. The voltage at node Y was Vinput - 0.3. The voltage at node X was 1.815 VDC regardless of the input voltage. This circuit is based on the RC oscillator in the Actel FPGA data book. They say that their formula
frequency = 1/(2.2*R2*C) (2)
is accurate for certain parameter values. When the lowest parameter values are substituted in equation 2 you get a frequency of 45 kHz. In other words, this oscillator is much too slow for our radio transmitter application. One could resort to using tuner diodes in parallel LCR resonant circuits or using transistor based oscillators. However, from the book by Rohde [2] it can be seen that this is a project all in itself.
Therefore we decided to use an IC. For our application we had to use a sillicon gate CMOS 74HCT4046A. This is a PLL IC with a VCO rated up to 20 MHz. Compare this to the standard CD4046 (Metal gate CMOS) PLL with a VCO rated up to "only" 1.6 MHz. The VCO requires three external components to set its behavior. They are shown below.
R1 and C1 set the center frequency f0 (in our case, 2.5 MHz) of the VCO. R2 is used to set the offset frequency (in our case, 1 MHz) with 0 Volts at the VCO input. The values of these resistors can be determined using the data sheets. However, using the Motorola data sheets this was not much more than a guess. We found a program to calculate these values in a Harris application note [3]. This has been translated into C and used to find the values. We tested these in the lab and we changed the values to approximate the required characteristic further. For more details see section 5.1.
3.1.3 Low Pass Filter
The Low Pass Filter (LPF) is used to filter the output of the phase detector to an average DC value for the VCO. It is used to filter out the harmonics, and only provide the DC value which is proportional to the phase error. As such the LPF is important in that it controls the behavior of the PLL to a large extent (factors such as damping, natural frequency, stability, and Pull-in range).
A passive lag filter can be used. However, an active LPF improves the PLL by introducing a pole at zero (an integrator). In practical terms, this means that the hold range and the pull-in range are theoretically infinite. When using a passive RC filter, the hold and pull-in range are finite, so if the frequency step applied to the phase detector is greater than the pull-in range the PLL will go out of lock. The active LPF filter characteristics are shown below.
To calculate the values of R1, R2, and C the design procedure in the book by Best [1] , Chapter 3 is followed.
1) The value N of the divide-by-N counter ranges from 10 to 40 in order to provide a frequency of 1 to 4 MHz in steps of 100 kHz. The PLL will be optimized (when the damping ratio
z= 0.7) for the divider ratioNmean =
Ö (Nmin)(Nmax) =Ö(10)(40) = 20
Since
z max / zmin = Ö (Nmax/Nmin) =2 < 3 this is acceptable.
2) Phase detector gain is approximately Vcc/(2*
p).Therefore, Kd = 5/6.28 = 0.8 V/ rad
3) The VCO operates linear for input voltages ranging from 1 Volt to 4 Volt when Vcc is 5V. This gives the following transfer characteristic:
This allows us to calculate the VCO gain factor K0.
K0=2*
p*(fmax-fmin) / (Vmax - Vmin) = 6.28*(3 MHz) /(3 V)K0= 6.3 rad/(s*V)
4) We now have to make some assumptions on the dynamic behavior of the PLL. If we were designing a PLL synthesized tuner for an FM receiver these specifications are important. However, in our case we are designing a frequency synthesizer and we can say that, for example, the PLL should lock within a short time, such as Tlock = 1 ms.
Then the natural frequency can be calculated as follows:
wn= 2*p / Tlock = 6300 rad/s
We must now check that the pull-out range
wpo is less than the reference frequency of 100 kHz.wpo= 5.78*wn*(z + 0.5) = 44,000 rad/s » 7000 Hz < 100 kHz
5) We can now calculate the filter components.
Using 
we get 
Since
z = wn*T2/2 => T2 = 2*z / wn = 222 ms
Selecting C = 0.33
mF we get:R1 =T1/C = 20 k
WR2 = T2/C = 680
WHence, the active filter implementation is shown below (as well as a passive lag filter implementation).
3.1.4 Divide-by-N Counter
The divide-by-N counter (or frequency divider) has to divide the input signal from 10 to 40 depending on the value that the user specifies. We considered two approaches:
1) Use fixed synchronous dividers in series. For example, have a divide-by-2 and a divide-by-3 and a divide-by-5 in series. At each divider output there is a multiplexer so that you can choose the undivided signal (bypass) or the divided signal. This implementation is then capable of dividing by 2, 3, 5, 6, 10, 15, 30. A simple controller would cycle through each of the states (in this case 7). Obviously, this implementation is rather limited in that the user can only select 7 different carrier frequencies. Another disadvantage is that the channel spacing is not the same. When it switches from N=15
to N=30 the frequency step might cause the PLL to unlock (although using an active filter this should not cause a problem). The advantage is that we’re guaranteed that this will work and it is synthesizable!
2) Use behavioral VHDL and split the circuit into a counter and a divider. The counter counts from 10 to 40. When the user presses reset, the counter will reset to a count of 25. When the user presses countup the count will be incremented by 1. If the count is 40 the count will stay at 40. If the user presses countdown the count will be decremented by 1. If the count is 10 the count will stay at 10.
The divider works as follows: When the user presses reset the divide count N will be set to 25. Everytime a pulse arrives at its input N will be decremented by 1. When the divide count has reached 0, the divider loads the new divide count from the counter "fsm".
The VHDL code for these two entities is shown below:
-- EE 552 PRoject-- Behavioral description of the up/down counter-- This counter counts up or down from Nmin to Nmax.-- The reset button sets the count to (Nmin + Nmax)/2 in the middle(Nmid)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;--use ieee.std_logic_unsigned.all;entity counter is port( load: out std_logic_vector(0 to 5); countup: in std_logic; countdown: in std_logic; reset: in std_logic);end counter;architecture behavior of counter is constant Nmin:std_logic_vector:="001010"; --10 constant Nmax:std_logic_vector:="101000"; --40 constant Nmid:std_logic_vector:="011001"; --25 begin process(reset, countup, countdown) variable N: std_logic_vector(0 to 5); begin if reset ='1' then -- Asyncronous reset N := Nmid; elsif (countup ='1') and N/=Nmax then N :=N +'1'; elsif (countdown ='1') and N/=Nmin then N := N -'1'; end if; load <= N; end process;end behavior;
3.2 Other Components
3.2.1 Crystal Oscillator
The Crystal Oscillator was implemented as described in the Actel FPGA data book. We had an 8 MHz Crystal available. The Crystal Oscillator worked very well. It generated a frequency of exactly 8.00 MHz. The circuit is shown in the figure below.
3.2.2 Prescalars
We required two prescalars in our design. The first one is required to divide the 8 MHz frequency down to the 100 kHz channel spacing frequency, i.e. it is required to divide by 80. The second prescalar is required to generate the 1 kHz data rate for the modulator. Hence an additional divide-by-100 prescalar is required. In the Actel FPGA data book there are various synchronous dividers shown on page 4-82. These dividers also have a 50 % duty cycle output.
To implement the divide-by-80 prescalar we used a divide-by-8 and a divide-by-10 in series. To implement the divide-by-100 prescalar we used two divide-by-10 synchronous dividers in series. For simulation purposes we added a clear to each D flip flop because the input depends on the output (which is undefined when starting simulation). The schematics for the divide-by-8 divider and the divide-by-10 divider are shown on the next pages. These schematics were converted to VHDL via the path: Schematics => mgc2edn => edn2vhdl => VHDL.
3.2.3 LED Display
Since the channel spacing is 100 kHz, the current divide ratio N corresponds directly to the carrier frequency in multiples of 100 kHz. Therefore, instead of making a complete frequency counter we can simply display the current divide ratio N. Since the number N is a 6 bit number we would have to do 6 variable Karnaugh maps. To avoid this, we implemented the display with 2 separate BCD counters. One 4 bit counter for displaying the least significant bit and one 3 bit counter for the most significant bit (since the MSB only goes from 1 to 4). In other words, we implemented a 2 digit LED display.
For this purpose we used 14 pins of the FPGA. The LED segments were common anode, so the diodes were driven active low. To avoid exceeding the maximum sink current of 20 mA for the Actel pins, we used 330
W resistors. The VHDL code is shown below.
-- This is the display driver for the radio transmitter-- The display driver outputs the current divide number and outputs it to -- the LED display. Depending on the quality of the PLL, the number of the fsm-- corresponds directly to the carrier frequency in multiples of 100 kHz.-- To simplify the karnaugh maps, 2 counters are used, one-- counter for each digit. The display is updated every time the division -- number changes.-- Notes: (1) the counter must be able to count up to 40 at least,-- hence it must be a 6 bit counter. To simplify implementation,-- we use a separate counter for each digit i.e. one 3 bit counter-- for the MSB and one 4 bit counter for the LSB. -- Therefore, the maximum possible displayed frequency is-- 7.9 MHz. The lowest possible displayed frequency is 0.0 MHz.-- (2) the display will have 2 digits only. -- (3) initially, the display will be implemented using 14 pins.---- DISPLAY FORMAT AND OUTPUTS:-- ______0_____ ______7____-- 1 | |2 8 | | 9-- | | | |-- -----3------ -----10----------- 4 | | 5 11 | | 12-- |___________| |___________|-- 6 13-- MSB LSBlibrary ieee;use ieee.std_logic_1164.all;--use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity displayc is port(countup: in std_logic; countdown: in std_logic; output0, output1, output2, output3, output4, output5, output6, output7, output8, output9, output10, output11, output12, output13: out std_logic; reset: in std_logic);end displayc;architecture LED of displayc isbegin pro1:process(countup, countdown, reset) variable count0: std_logic_vector(0 to 3); variable count1: std_logic_vector(0 to 2); begin if reset ='1' then -- initialize signals, display 25 count1 :="010"; count0 :="0101"; -- output <="01000100010100"; output0 <='0'; output1 <='1'; output2 <='0'; output3 <='0'; output4 <='0'; output5 <='1'; output6 <='0'; output7 <='0'; output8 <='0'; output9 <='1'; output10 <='0'; output11 <='1'; output12 <='0'; output13 <='0'; elsif countup ='1' then count0 := count0 + '1'; if count0 ="1010" then count0 :="0000"; count1 := count1 + '1'; end if; elsif countdown='1' then if count0 = "0000" then count0 :="1001"; count1 := count1 -'1'; else count0 := count0 -'1'; end if; end if; -- update display output0 <= not (count1(1) or (count1(0) and count1(2)) or (not count1(0) and not count1(2))); output1 <= not((not count1(1) and not count1(2)) or (count1(0) and not count1(1)) or (count1(0) and not count1(2))); output2 <= not(not count1(0) or (not count1(1) and not count1(2)) or (count1(1) and count1(2))); output3 <= not((count1(0) and not count1(1)) or (not count1(0) and count1(1)) or (count1(1) and not count1(2))); output4 <= not((count1(1) and not count1(2)) or (not count1(0) and not count1(2))); output5 <= not(count1(0) or count1(2) or not count1(1)); output6 <= not((count1(0) and not count1(1) and count1(2)) or (not count1(0) and not count1(2) or (not count1(0) and count1(1)) or (count1(1) and not count1(2))); output7 <= not(count0(0) or (count0(1) and count0(3)) or (not count0(0) and count0(2)) or (not count0(0) and not count0(1) and not count0(3))); output8 <= not(count0(0) or (not count0(2) and not count0(3)) or (not count0(2) and count0(1) or (not count0(3)
and count0(1))); output9 <= not(count0(0) or not count0(1) or (not count0(2) and not count0(3)) or (count0(2) and count0(3))); output10 <= not(count0(0) or (not count0(2) and count0(1)) or
(count0(2) and not count0(3)) or (not count0(1) and count0(2))); output11 <= not((count0(2) and not count0(3)) or (not count0(3) and not count0(1))); output12 <= not(count0(3) or not count0(2) or count0(1)); output13 <= not(count0(0) or (not count0(3) and not count0(1)) or (not count0(2) and count0(3) and count0(1)) or
(count0(2) and not count0(3)) or (count0(2) and not count0(1))); end process;end LED;
Note that the Karnaugh derivations for the boolean equations are shown in the appendix.
3.2.4 Output Low Pass Filter
Since the output of the modulator is a digital signal (square wave), we have to filter it in order to transmit the fundamental of the modulator output signal. The purpose of the LPF is to filter out all the other harmonics before the signal goes to the antenna. For this purpose we designed a passive LCR filter with a cutoff frequency of 4 MHz.
To do this we used Chapter 11 of Sedra & Smith, [4] as a reference.
The transfer function of a second order LPF is:
(4)
and the transfer function for the LCR resonator is
(5)
From equation (4) it can be seen that the DC gain is 
. Using the fact that the DC gain is 1 and f0 = 4 MHz we get that a0 = w0
. Now selecting a Q of 0.7 gives R = 560 W.
The resulting filter is shown below.
For the antenna we used a standard AM loop antenna (impedance about 50
W). We used 5 FPGA output pins to drive the antenna to ensure we did not exceed the current rating of the FPGA output pins (=20 mA max.). Since we did not worry about matching the modulator output impedance with the antenna impedance, the transmitted power was very small. The range of transmission was only a few meters.
3.3 Modulator
The modulator was designed, implemented and tested using VHDL in the form of a finite state machine. A total of nine states were used to create this block of the radio transmitter design and the VHDL code is listed on the following page. Essentially, if the first detector was enabled, the modulator emitted a 001111. The two 0 framing bits were followed by the code of the first detector. If the second detector was enabled, a sequence of 001101 was emitted. If both were enabled simultaneously or sequentially, the modulator emitted a 001111001101 ... . This code was emitted at a data rate of 1 kHz as per the 8 MHZ crystal oscillator frequency scaled down by a factor of 80. This signal was then anded with the carrier frequency set between 1 and 4 MHz. The resulting signal was a form a amplitude modulated on-off keying (OOK) that could be tested using a simple AM radio. Five output pins were tied together and directed this signal through a filter and on to the AM loop antenna for transmission.
To verify that our design was functioning correctly we simulated each component seperately both post-synthesis and back-annotated. We also simulated the complete system. To do this we had to add an asynchronous clear to both prescalars and the phase detector. The results of the back-annotated simulation have been submitted as part of the Simulation Documentation. This report is included in the Appendix.
The main purpose of this section is to highlight waveforms that show:
(a) The display driver simulated correctly (even back-annotated).
(b) The programmable divider simulated correctly (even back-annotated).
The next page shows the appropriate waveforms. In particular, it shows that when countup is pressed the divide ratio N is incremented by 1. It shows that the divider output ‘testdiv’ is the input ‘icvco’ divided by N. The waveforms also show that the LED display is updated correctly when countup is pressed. (Note: these waveforms do not show whether countdown works; this has been tested as well and works exactly the same way).
Our strategy for design verification has been to test the components seperately first. Then after the whole design was compiled and laid out by designer, we used the extracted waveforms to verify that the dividers, the display, and the phase detector were functioning correctly. The modulator has been tested for all cases: detector_1 off, detector_1 on, detector_2 on, both detectors on, both detectors off.
5 Testing
5.1 VCO Testing
As described in section 3.1.2, the Voltage Controlled Oscillator required further testing for achieving the required characteristic from 1 to 4 MHz. (The testing of the ‘discrete’ VCO has already been described in 3.1.2). The results are shown in the table below.
We used the last entries in the table: R1 = 15 k, R2 = 130 k, C1 = 122 pF. Using these values we obtained a center frequency of 2.515 MHz when Vin is 2.5 V.
5.2 Complete System Test Results
We have breadboarded the complete system for testing and demonstration purposes. For our project, the IC tester was not useful. In the first stages of testing we tested the system in an open loop configuration. In other words, we adjusted the input voltage to the VCO manually using a power supply. These are our observations:
a) The modulator worked 100 %. By reducing the time scale on the oscilloscope to the order of a millisecond we could observe the frames as well as the 4 bit words send out depending on which detector was enabled. Also the data rate was 1 kHz, which shows that the prescalars were all working fine. If a detector was enabled and subsequently disabled the modulator would continue sending the appropriate code word even though the detector was disabled. If both detectors were disabled and reset was pushed, the output of the modulator would be ‘0’. Also, if both detectors were enabled, the output of the modulator would be 001111001101 as required.
b) The phase detector worked 100 %. By observing the output of the phase detector while varying the VCO input voltage, we were able to vary the duty cycle of the phase detector output from 0 to 100 %. The phase detector output was usually at a frequency of 100 kHz. Some of the measurements are presented in the table below.
c) There are problems with the counters in the display and the divider components. When either countup or countdown is pressed the counters will count to a random value.
We did not add gates for debouncing these two switches in the FPGA, however, even when we used 555 monostables to provide a real short pulse, the counters would still count to a random value (however, they would count for a shorter time). The problem seems to be that the counters count as long as either countup or countdown is high, i.e. they are not rising edge triggered. In entity fsm and entity displayc they have been programmed as: if(countup =’1’) then . This was done in order to make the code synthesizable ( can’t have concurrent rising_edge statements). However, when we did the back- annotated simulation it appeared as if both counters were edge triggered (see section 4). Thus, it appears as if the simulator tricked us into believing that it worked.
We have also tried the following circuit in order to obtain short pulses (shorter than when using the 555 timer).
We have varied the number of inverters in order to obtain various pulse widths. However, the counters still did not increment by 1.
The circuit worked correctly when reset was pressed. The divider did divide the vco output by 25 and the LED display displayed the number 25. The problem is due to the operation of the counters. The combinational logic in the display component was correct since the LED’s always displayed a valid digit. Also the divideN entity worked correctly (the counter is in entity counter). Some results measured using the testdiv pin are shown in the table below.
The results in the table show that the divide ratio N is variable, however, the problem is that the counter in entity count is not rising_edge triggered and hence if the user presses countup or countdown N is incremented by a random number. Hence the problem is confined to the entity count and the counter in entity displayc.
d) The closed loop PLL system worked 50 %. Using the passive lag filter described in section 3.1.3 the VCO input voltage was obtained from the filter output (instead of an external power supply). When reset is pressed the carrier frequency adjusts to 2.50 MHz. This proves that a) the phase detector works, b) the loop filter works, c) the variable divider works, c) the prescalars work. In other words, it proves that the basic PLL system works. However, when either countup or countdown is pressed, the divide ratio N is incremented by a random number and hence the carrier frequency is also incremented randomly. Sometimes the increase in N would be too large and the PLL would go out of lock (we’re using the passive lag filter here).
CONCLUSION: The system works correctly except for the counters in entity counter and in entity displayc. The problem is most likely due to the fact that they are not rising_edge triggered.
6 Conclusions
This project was an interesting exercise in digital system design. We learned a lot about using Mentor Graphics tools for simulation, schematic capture, and VHDL. We also learned about synthesis tools and the typical design flow.
We also became familiar with the Phase-Locked Loop and its many interesting applications. It is used a lot in communication circuits such as demodulators, clock recovery, frequency synthesizers and also in other areas such as motor speed control.
It was nice to see that most parts of the system worked correctly. We were able to demonstrate the modulator and the actual transmission of the signal by using an AM radio. Nevertheless, it was a dissappointment that the counters did not work correctly. What we learn from this is that it is very important to think of a low level hardware implementation while programming the high level VHDL. If you know the hardware level implementation you should always use this (using schematics) or structure the VHDL accordingly. This way you know that the code is synthesizable and you know that it will (or should) work.
It is important to use all the I/O pins available, even if the actual project does not require it. The other pins can be used for testing. For our project, the testdiv and testvco pin were very useful. As Dr. Elliott pointed out we could have saved two pins by simply feeding the VCO IC output to the vco1 pin. This would have made the pins selectvco and icvco redundant, as well as the mux inside the FPGA.
7 References
1. Best, Roland E. Phase-Locked Loops Theory, Design, Applications 2nd edition, Mc Graw Hill, 1993 (This is the Best book on PLL’s!)
2. Rohde, Ulrich L. Digital PLL Frequency Synthesizers, Theory and Design Prentice-Hall, 1983.
3. Austin, W.M.A. CMOS Phase-Locked Loop Applications Using the CD54/74HC/HCT4046A and CD54/74HC/HCT7046A. Harris Semiconductor, Application Note AN8823.1.
4. Sedra & Smith Microelectronic Circuits 3rd edition, Chapter 11.
5. Motorola Semiconductor Technical data, MC74HC4046A data sheet.
6. Actel FPGA data book.
7. Notes provided by Dr. Elliott.
8 Appendix
In the appendix we have included the following information:
1) VHDL code that was not already presented in this report
2) LED display Karnaugh maps
3) Simulation documentation