-- by Dan Kotylak 
-- part of the digital self regulating humidifier

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;

entity func is 
	port (clock, reset, en: in std_logic;
			freq_value : in std_logic_vector(8 downto 0);
			humid_value : out std_logic_vector(6 downto 0)
	);
end func;

use work.subtractor.all;
use work.bitreg7.all;


architecture mixed of func is

component subtractor  
	port (A,B: in std_logic_vector(9 downto 0);
			data_out: out std_logic_vector(9 downto 0)
	);
end component;

--register for pipelining

component bitreg7 
	port(clock, reset, en: in std_ulogic;
			D: in std_logic_vector(6 downto 0);
			Q: out std_logic_vector(6 downto 0)
	);
end component;


signal int_connect : std_logic_vector(9 downto 0);
signal humid_connect : std_logic_vector(6 downto 0);
constant sub_value1 :std_logic_vector(9 downto 0):="0110000010";
signal freq_value_sin: std_logic_vector(9 downto 0);
signal sub_val2: std_logic_vector(9 downto 0);

for all:subtractor use entity work.subtractor(behaviour);
for all:bitreg7 use entity work.bitreg7(behaviour);


begin

sub_val2<=sub_value1;
sub1:subtractor port map(A=>sub_val2,B=>freq_value_sin,data_out=>int_connect);
reg1:bitreg7 port map(clock=>clock,reset=>reset,en=>en,D=>humid_connect,Q=>humid_value);

CONGEN1: for i in 0 to 8 generate
	freq_value_sin(i)<=freq_value(i); 
freq_value_sin(9)<='0';
end generate;

CONGEN:for i in 0 to 6 generate
	humid_connect(i)<=int_connect(i);
end generate;

end mixed;