-- the higheset level entity for the digital humidifier
-- Adrian Chan and Dan Kotylak

library ieee;
use ieee.std_logic_1164.all;

-- includes for our lower level design
-- (actmap seems to need the .all, but da doesn't like it)
use work.comparator_module.all;
use work.keypad.all;
use work.mainfsm.all;
use work.freqdet.all;
use work.func.all;
use work.hex2bcd.all;
use work.my_dff_e.all;

entity humidifier is
   port(
      clock, reset: in std_logic;
      freq_in : in std_logic;
      humid: out std_logic;
      keypad_row: inout std_logic_vector(3 downto 0);
      keypad_column: in std_logic_vector(2 downto 0);
      keypad_MSD, value_LSD, value_MSD: out std_logic_vector(3 downto 0);
      keypad_LSD: inout std_logic_vector(3 downto 0);
      fval1 : out std_logic_vector(8 downto 0);
      f_value : out std_logic_vector(6 downto 0);
       	
      -- master clock with crystal
      in_mclk : in std_logic;
      out_mclk : out std_logic;
      out_mclk_sq : out std_logic;		

      -- On chip RC oscillator (for sensor input)
      r1_in: in std_logic;
      r2_out, cap_out: out std_logic

   );
end humidifier; 


architecture structure of humidifier is

attribute donttouch : string;
attribute donttouch of mclk_inv: label is "true";
attribute donttouch of fclk_inv1: label is "true";
attribute donttouch of fclk_inv2: label is "true";
attribute donttouch of fclk_inv3: label is "true";
attribute donttouch of outbuf_out_sq : label is "true";

-- component declarations
component INBUF
	port(
		PAD : in std_logic; Y : out std_logic) ;
end component;

component INV 
   port(
      A                              :  in    STD_LOGIC;
      Y                              :  out   STD_LOGIC);
end component;

component OUTBUF
   port(
      D                              :  in    STD_LOGIC;
      PAD                            :  out   STD_LOGIC);
end component;


component my_dff_e
   port(
      clock,clear,enable,D : in std_logic;
      Q : out std_logic
   );
end component;

component comparator_module 
   port(
      clock,reset,latch_data,latch_freq : in std_logic;
      keypad_in,sensor_in : in std_logic_vector(6 downto 0);
      below : out std_logic
   );
end component;

component keypad 
   port(
      clock,reset,new_data_ack: in std_logic;
      new_data,data_enable : out std_logic;
      keypad_MSD : out std_logic_vector(3 downto 0);
      keypad_LSD : inout std_logic_vector(3 downto 0);
      keypad_column : in std_logic_vector(2 downto 0);
      keypad_row: inout std_logic_vector(3 downto 0);
      num : out std_logic_vector(6 downto 0)
   );
end component;



component mainfsm 
   port(
      clock,reset,new_data,below,newfreq_endone,newfreq_getdone,gt10,data_enable : in std_logic;
      humid,new_data_ack,newfreq_en,freq_latch,newfreq_get,enablesub,enablemux,resetcount,latchop,
      det_latch,func_latch,humid_en : out std_logic
   );
end component;


component freqdet 
   port(
      frequency_in, new_freq_enable,new_freq_get, clock, latch_freq, reset, lut_latch: in std_logic;
      new_freq_en_done, new_freq_get_done: out std_logic;
      frequency_value: inout std_logic_vector(8 downto 0)
   );
end component;

component func  
   port (
      clock, reset, en: in std_logic;
      freq_value : in std_logic_vector(8 downto 0);
      humid_value : out std_logic_vector(6 downto 0)
   );
end component;

component hex2bcd 
	port (
			clock, enablemux, enablesub, enablelatch, reset,resetcount : in std_logic;
			greaterthan: out std_logic;
			bit_input7 : in std_logic_vector(6 downto 0);
			bit_outputL4, bit_outputH4	: out std_logic_vector(3 downto 0)
	);
end component;
	
-- signals for the control lines to data path
signal new_data,below,newfreq_endone,newfreq_getdone,gt10,data_enable,
new_data_ack,newfreq_en,freq_latch,newfreq_get,enablesub,enablemux,resetcount,latchop,
det_latch, func_latch,humid_D,humid_en : std_logic;

-- signals for the datapath

-- from keypad to compare module
signal num: std_logic_vector(6 downto 0); 

-- from sensor path to compare module and hex2bcd
signal value: std_logic_vector(6 downto 0);

--  from frequency determiner to function
signal frequency_value: std_logic_vector(8 downto 0);

signal freq_int: std_logic;

-- signals for clock stuff
signal to_mclk_inv, from_mclk_inv, to_fclk_inv1, from_fclk_inv1, from_fclk_inv2, from_fclk_inv3 : std_logic;

for all: keypad use entity work.keypad(structural);
for all: comparator_module use entity work.comparator_module(struct);
for all: mainfsm use entity work.mainfsm(mixed);
for all: freqdet use entity work.freqdet(mixed);
for all: func use entity work.func(mixed);
for all: hex2bcd use entity work.hex2bcd(mixed);
for all: my_dff_e use entity work.my_dff_e(behavioural);

begin

freq_inbuf:INBUF port map(PAD=>freq_in,Y=>freq_int);

mainfsm1:mainfsm port map(
      clock=>clock,reset=>reset,new_data=>new_data,below=>below,newfreq_endone=>newfreq_endone,
	   newfreq_getdone=>newfreq_getdone,gt10=>gt10,data_enable=>data_enable,
      humid=>humid_D,new_data_ack=>new_data_ack,newfreq_en=>newfreq_en,freq_latch=>freq_latch,
		newfreq_get=>newfreq_get,enablesub=>enablesub,enablemux=>enablemux,resetcount=>resetcount,
		latchop=>latchop,det_latch=>det_latch,func_latch=>func_latch,humid_en=>humid_en);

my_dff_e0: my_dff_e port map(
		clock=>clock,
		clear=>reset,
		enable=>humid_en,
		D=>humid_D,
		Q=>humid
		);

keypad1:keypad port map(
      clock=>clock,reset=>reset,new_data_ack=>new_data_ack,
      new_data=>new_data,data_enable=>data_enable,
      keypad_MSD=>keypad_MSD,
      keypad_LSD=>keypad_LSD,
      keypad_column=>keypad_column,
      keypad_row=>keypad_row,
      num=>num);

comparator_module1: comparator_module port map(
      clock=>clock,reset=>reset,latch_data=>data_enable,latch_freq=>freq_latch,
      keypad_in=>num,sensor_in=>value, 
      below=>below);

freqdet1: freqdet port map(
		frequency_in=>freq_int,new_freq_enable=>newfreq_en,new_freq_get=>newfreq_get,
		clock=>clock,latch_freq=>det_latch,reset=>reset,
		new_freq_en_done=>newfreq_endone,new_freq_get_done=>newfreq_getdone,
		frequency_value=>frequency_value,lut_latch=>func_latch);

fval1<=frequency_value;
f_value<=value;

func1: func port map(
		clock=>clock,reset=>reset, en=>func_latch,
		freq_value=>frequency_value,
		humid_value=>value);

hex2bcd1: hex2bcd port map(
			clock=>clock, enablemux=>enablemux,enablesub=>enablesub,enablelatch=>latchop, 
			reset=>reset,resetcount=>resetcount,
			greaterthan=>gt10,
			bit_input7=>value,
			bit_outputL4=>value_LSD, bit_outputH4=>value_MSD);


-- clocking stuff

-- master clock with crystal
inbuf_in_mclk: INBUF port map(PAD=>in_mclk, Y=>to_mclk_inv);
outbuf_out_mclk : OUTBUF port map(D=>from_mclk_inv, PAD=>out_mclk);
mclk_inv : INV port map(A=>to_mclk_inv,Y=>from_mclk_inv);
outbuf_out_sq : OUTBUF port map(D=>from_mclk_inv, PAD=>out_mclk_sq);


-- frequency in with cap (sensor input)
inbuf_r1_in: INBUF port map(PAD=>r1_in, Y=>to_fclk_inv1);
outbuf_r2_out: OUTBUF port map(D=>from_fclk_inv3, PAD=>r2_out);
outbuf_cap_out: OUTBUF port map(D=>from_fclk_inv2, PAD=>cap_out);

fclk_inv1: INV port map(A=>to_fclk_inv1,Y=>from_fclk_inv1);
fclk_inv2: INV port map(A=>from_fclk_inv1,Y=>from_fclk_inv2);
fclk_inv3: INV port map(A=>from_fclk_inv2,Y=>from_fclk_inv3);

end structure;