-- EE 552 (A1)
-- Digital Self-regulating Humidifier
-- compare_module.vhd - compare module top level
--
-- Adrian Chan & Dan Kotylak
-- 97/11/04

library ieee;
use ieee.std_logic_1164.all;

use work.my_reg7.all;
use work.set_pre.all;
use work.comparator.all;
 
--use work.my_reg7;
--use work.set_pre;
--use work.comparator;

entity comparator_module is
   port(
      clock,reset,latch_data,latch_freq : in std_logic;
      keypad_in,sensor_in : in std_logic_vector(6 downto 0);
      below : out std_logic
   );
end comparator_module;

architecture struct of comparator_module is
   signal set_compare,meas_compare : std_logic_vector(6 downto 0);

   component my_reg7
      port(
         D : in std_logic_vector(6 downto 0);
         Q : out std_logic_vector(6 downto 0);
         clock,load,clear : in std_logic
      );
   end component;

   component set_pre
      port(
         D : in std_logic_vector(6 downto 0);
         Q : out std_logic_vector(6 downto 0);
         clock,load,preset : in std_logic
      );
   end component;

   component comparator
      port(
         measured,set : in std_logic_vector(6 downto 0);
         below : out std_logic
      );
   end component;


   for all:my_reg7 use entity work.my_reg7(behaviour);
   for all:set_pre use entity work.set_pre(behaviour);
   for all:comparator use entity work.comparator(behavioural);

begin

   humid_meas: my_reg7 port map(
      D=>sensor_in,
      Q=>meas_compare,
      clock=>clock, 
      load=>latch_freq,
      clear=>reset
   );

   humid_set: set_pre port map(
      D=>keypad_in,
      Q=>set_compare,
      clock=>clock,
      load=>latch_data,
      preset=>reset
   );

   compare0: comparator port map(
      measured=>meas_compare,
      set=>set_compare,
      below=>below
   );
end struct;