The main state machine is the "brains" of our design. It controls the lower level modules (specifically coordination and data transfer). It also outputs a control signal which can be used to control a humidifer unit.
For the some of the control signals (eg humidifier control), we needed the signal to hold its value until it was changed. We tried to implement this by using the properties of the VHDL case statement. Basically, we read in the Actel VHDL documentation that a signal that is not assigned in every situation will hold its previous value. This did not work as expected. To fix the problem, we explicitly used a D flip-flop to hold the value of the control signal.
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