December 2, 1997

This report culminates the design component of ee552. This course gave us the opportunity to select a project, design it, and build it. Our design is centered around a 44-pin Actel 1020B field programmable gate array.

Through extensive brainstorming, we decided to construct an alarm clock with standard features like a snooze button, perfect it, and then if there was time, add additional features. As such, we dove into the design process, which consisted of late nights in the lab and what seemed like endless simulations, in the beginning of September. Due to constraints of time and chip limitations, what started as an alarm clock finished as what we call a 5-minute egg timer.

User inputs include a start button, a reset, and a detector switch. The start button and the detector switch control the alarm after it turns on. The clock and alarm displays are displayed on four 7-segment LED’s.

Included here are details, results, diagrams, and documented VHDL of our design. As well, in paper copies of our presentation slides have been included in the appendix.

We were disappointed that, due to constraints of space and time, we could not implement the design we originally came up with, however, we both agree this course is an asset providing valuable learning experience which was well worth the four months.

Abstract page 2

Introduction page 4

Overview page 4

Design Details page 5

IC Detail page 8

IC Tests page 10

Design Verification page 11

Design Documentation page 11

Appendix A—Block Diagrams page 12

Appendix B—Simulations page 13

Appendix C—Documentation page 14

Appendix D—Presentation page 15

One predominant aspect of this course is the usage of Mentor Graphics and Actel Designer CAD tools in digital design. Mentor provides two tools for implementation of digital circuitry. One being schematic capture and the other Very High Speed Integrated Hardware Description Language (VHDL). Both serve the same purpose in that they describe both the behaviour and the structure of the design, however the former is graphic based and the latter is code based.

This report culminates our design of a digital timer which is achieved almost entirely in VHDL. This is accomplished by having numerous levels of behavioural code before tying it together with top level structural code.

After testing and verifying our code’s functionality, it is burned onto an Actel chip. Then, this, together with some external circuitry, establishes the timer.

Our total design was all implemented in VHDL. Not having known the limitations of the Actel chip, our timer actually began as a basic alarm clock. We decided to keep the design simple and then depending on time, add more features once we had working simulations. In addition to the clock, a basic alarm in the market might include a snooze bar and increment and decrement buttons to adjust the clock time. We included all these properties into our design however, rather than having a standard twelve hour clock, ours was a 24 hour clock and in place of a snooze bar there was a photo detector and a light source. We thought this would be ideal for the kitchen. For example, place the light detector and transmitter in a doorway of and then set the alarm for a certain time. Then, when the alarm sounds, simply by passing through the doorway, the alarm goes into snooze mode to switch off whatever was being timed. After the alarm is initially triggered, the snooze cycle continues until the main switch has been turned off. A block diagram of this initial design can be seen under Figure 1 of the Appendix A.

Our initial design had a 1 MHz external clock fed to a clock divider inside the chip to generate different clock pulses for different entities. This entity, called clockgen, takes the 1 MHz clock and splits it into clocks with output periods of 0.5 seconds, 1 second, and 60 seconds.

Adjusting both the clock and the alarm set time works the same way. So by port mapping differently in the top level code, only one entity had to be written for this process. This entity had four inputs including one for the 0.5 second clock. The other three inputs are an add signal, a subtract signal, and a signal called adjust. Its output is a 16-bit vector since each digit of the time is represented with a four-bit vector. When add (or subtract) is pressed, the minute digits of the time increment (or decrements) once per each clock pulse. When add or subtract and adjust are held down simultaneously the hour digits of the time changes depending on the button pressed. As well as being displayed on the LEDs, the 16-bit vector of the alarm adjust is then compared to see whether the conditions for the alarm to turn on are met. The output of the clock adjust is input to an entity called increment which is the essence of the clock and the output of the alarm adjust is input to an entity called compare3 to be compared to determine if the alarm should be sounded or not.

The basis of the clock is in the entity increment. It takes as inputs a 16-bit vector from the clock adjust and a clock pulse which changes every 60 seconds from the clock generator, clockgen. With each clock pulse, a minute is added to the clock time. This output is sent to entities where it is compared and where it is displayed.

Due to the fact the LEDs which make up the display of the alarm clock are 7-segment LEDs, each four bits of the 16-bit vectors to be displayed must be converted to 7-bit code to either enable or disable a particular segment. The decoding is done by an entity called bcd and its outputs go to a multiplexer called selector which operates at a high frequency, outputting to one external display at a time. This is so in order to reduce the number of outputs coming from the chip itself.

In order to determine whether the conditions to turn on the alarm are met, a series of comparisons must be done. For the alarm to turn on, the main switch must be on, the signal match, which is output from compare3, must be high and there must be a high signal coming from the photo detector. The entity output tests for these factors before sending a 1 to turn the alarm on. Before the alarm initially turns on (before there is a high to low transition from the light detector) the entity compare3 compares the clock time with the alarm time. Once the two are equal, match goes to ‘1’. After a transition at the light detector, the clock time is compared with 16-bit vector coming from the entity add2 which is activated on that transition.

The snooze mode operates on a two minute cycle. As soon as there is a change in signal from the detector, add2 takes the clock time and adds two minutes which is then fed to compare. This continues until the main switch has been switched off.

As we found out after completing our simulations, this original design was too large to fit on the chip, Actel 1020B, we were using which can only fit 547 logic modules. We had 1878.

We reduced our design to a five minute timer. Rather than having user input to set the alarm time, five minutes was hard coded as the alarm time in VHDL. Since it is only a five minute timer, we only needed four 7-segment displays. Two each for the alarm and the clock. The system has a global reset and a global clock which is generated by a 555 timer operating in the astable mode with a period of 8.33ms. Before the system is started, reset must be toggled so that the clock time is set to zero. There is a main switch is which starts the clock. When start is ‘1’ the clock increments from 00 to 05. Compare3 works in the same way however it only compares two vectors: the one which represents five minutes coming from the alarm time and the clock time. Again, when there is a match, the signal match changes to ‘1’ and this is output to the entity output to test for a certain set of conditions.

Since our design is not large, we chose to use the 44-pin Actel 1020B which has the capacity to fit 547 logic modules. Our external circuitry consists of a 555 timer operating in astable mode as our system clock, two LEDs (one acting as the light source and the other the alarm), 3 dip switches (one each for main, reset, and the detector). We decided against implementing the alarm and the light detector/transmitter due to time constraints. The dip switches do not need debouncing since we are not using them to create a pulse.

Our design was approached from a bottom-up format. We coded from the lowest level (bcd decoder) up to the top-level code, which linked all our entities together. Our code, as seen in Appendix B, consists primarily of if statements. This proved to be a major stumbling block upon synthesis since if statements consume a lot of modules, which is why we had to go through two stages of cutting. The clock generator, the entity split the clock to give different pulses used up 597 modules was the first to be cut and replaced with an external component. Since we only needed a rising edge, a 555 timer (figure 1) which outputs a single pulse at a specified frequency was used. We wanted a period of 8.33ms with a 50% duty cycle. So, T_rise and T_fall must be equal, therefore R_B»R_A. So, picking C to be 0.1m F and R_A=1kW

A pulse of period 8.33ms could not be realized using 60kW because of component tolerances. So, we arbitrarily increased R_B’s values to 56kW to give us the correct pulse.

This pulse is used as our system clock. Then, rather than having a clock divider, if an entity operated at a certain clock period, our code would loop a certain number of times. For example, in the entity increment, it must increment 7200 times before it proceeds further. This number multiplied by the clock period gives 60 seconds. So, it is clear that the clock increments once every minute.

We subsequently decided to simplify our design by cutting the snooze feature which means cutting add2. However, deleting add2 and clockgen only reduced our module number to 737. Here, we arrived at our second reduction stage, which turns out to be our final design.

Initially, we did not have a selector to mux the output out to the 7-segments. Because of this, we exceeded the number of I/O pins. To reduce the number of pins needed to go out to the 7-segment LEDs, case statements were written so that 7-bit vectors would out to the LED’s one at a time.

Altogether, before optimization, the area of our design was 518 modules large with the longest path being 331.8 ns. One trade-off of having a faster circuit is there are more modules perhaps due to pipelining and adding more flip-flops. After flattening, our longest path was reduced to 267.0 ns, however, the number of logic modules increased to 532.

In the beginning, we had a lot of problems back annotating since a lot of VHDL, unless written with hardware in mind, cannot be represented in hardware. For example, statements like "else" and "wait" could not be synthesized. We discovered that without a global reset, the design will not work after back annotation since unknown values get stuck in the circuits causing error. A global reset initializes all values to zero upon toggling. Also, in entities with if statements, all conditions must be stated in the VHDL otherwise, after back annotation, errors arise upon simulation. We concluded that this is possibly because the hardware does not know what step to take next. When all conditions are stated, if one is not satisfied, the next is evaluated until one statement is fulfilled causing no confusion within the circuit.

We ended up using the 44 pin Actel 1020B PLCC FPGA since our IO pins only added up to 17. In the beginning, we were ambitions and had problems fitting our design onto the chip, but after scaling down our design, it was not a big problem.

The final design, optimized for speed, used up 97% of the chip’s area.

Note: NC represents "Not connected"

see also figure 1. 555 timer

By optimizing for speed, we bettered the longest path time by 20% however, our total area went up 3%.

7-Segment Displays

For the displays we used common cathode 7-segments part 74A and the segments correspond to the above diagram, figure 2.

Having a simple circuit meant having simple tests. The first step we took was to test the 555 timer. Due to component tolerances, the value which was calculated did not give the desired pulse duration and so by trial and error we decreased the capacitor values until T=8.37ms giving a difference of 0.02ms of which we thought, since our timer does not run for very long, was negligible.

Before connecting any LEDs, we connected the 555 timer to pin 33 and the dip switches to its respective pin on the Actel chip. Using a stop watch, we timed the circuit as we ran it. Each time a minute hit, we used a wire probe to test whether there was a change of signals from ‘0’ to ‘1’.

After establishing the chip’s functionality, we connected all the externals (i.e./ putting in LEDs for the signals sound and light and connecting all the 7-segments). Surprisingly, the 7-segments had enough current to drive them albeit the last two 7-segments of four were a little dim. The LEDs of sound and light, though, had too much current so we had to build a current divider to prevent blowing the LEDs. We used resistor values of 220W . The circuit can be seen as follows in figure 3.

The rest of the circuit provided no major problems as our

Please see Appendix B.

Please see Appendix C.