Tutorials on Using Publicly Available Tools

Step-by-Step Procedure

1. Design Architect
   Use the design architect to compile and simulate the VHDL coding. But first, need to set up the environment for the current directory first
   
   %setenv MGC_WD `pwd`
   %setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini
   %da&
   
   Once the designer architect is open, you can open your VHDL files to compile and simulate
   

   (toolbar)File => Open => VHDL

   Type in the VHDL filename in the VHDL Source Name field.
   Click okay button
   

   (toolbar)Compile => set_options

   Select Explicit Scoping and Constraint Checking
   Specify the library "Work" in the current library
   Click okay button
   

   (toolbar)Compile => Compile

   Then, a screen will pop up to show whether you have errors or not. If there is error, you can use the highlight button to highlight that error and then correct it. Remember to save the file after you have made the corrections. If there is no error, it will say Quickhdl compilation completed successfully and you are ready to simulate the VHDL coding.
   
   
2. Quicksim
   To run qhsim for simulation,

   (toolbar)QuickHDL => Simulate

   A screen will pop up and specify the corresponding library "work" and the time units you needed.
   Click okay button
   The startup window for qhsim will pop up. Choose the entity that you want to simulate.
   

   (Qhsim toolbar)View => Signals

   This will bring up the signal screen that list out all the signals.
   Then, you can display the waveform by

   (Signals toolbar)Wave => Signal in design

   Then, you can click the run button to simulate the design. You can also change the default run time which is 100ns by

   (Qhsim toolbar)Options => Properties

   Then, you can change the default run and the iteration limit fields to what you want.
   Besides, you may force a value to a given siganl by first select the signals and then,

   (Signals toolbar)Force => Force

   You can then type in the value you want in the Value field.
   Besides, if you have clock, you may also want to force it in the qhsim prompt. For example,

   force clock 0 20,1 40 -r 40

3. Actmapw
   After VHDL simulation, you can convert the VHDL files into EDIF netlist (.edn) and optimize for size/speed and generate .edo files.

   % actmapw

   (toolbar)File => New Design

   Then, select the VHDL file that you want to use.
   An ACTmap VHDL compiler screen pops up and choose the following:

   Source Design: Get your file
   Source Format: VHDL
   Family: ACT1
   Effort: High
   Mode: chip
   Max Fanout: 10
   Minimize: Area
   flatten

   Then, click run button
   This will generate .edn and .aml files and you can see find out many modules, IO pins and other useful information.
   Also, you can further optimize for speed by using the Netlist Opt. This will generate a .edo file instead of .edn.
   
   
4. Designer
   Now, you are ready then to convert the code into chip. First, make a copy of the .edn that has just created (I assume set_time.edn). Then, create a structural VHDL.

   %cp set_time.edn set_time_str.edn
   edn2vhdl fam:act1 set_time_str

   Now, start the designer
   

   designer

   (toolbar)Options => Setup Design

   Type in the Design name in the name field and choose Familty ACT1
   

   (toolbar)Options => Set Die and Package

   A Device Selection menu will pop up and select the part list you required.
   Then, the Operation Conditions meny will pop up. Choose the followings:

   Speed Grade: STD
   Temperatue: COM
   Voltage: COM
   

   Then, you can import your file.

   (toolbar)File => Import => Netlist File

   Choose New
   A Import Netlist screen pop up and choose the following:

   Netlist Type: EDIF
   File Name: Select your own filename
   Edif Flavor: MGC
   Naming Style: Generic
   

   Click OK button
   The file will then be import.
   Click the compile button
   Click the layout button and choose the following:
   

   Mode: Standard
   Incremental: OFF

   Click the fuse button and choose your filename and a .afm file will be created.
   For back annotate simulation, click the extract button A extract dialog box will pop up and choose the following:

   Extracted File Directory: .
   Extracted File Name: select your file name
   CAE: GENERIC

   Click OK button.
   A status box will pop up and choose the following:
   

   Speed: STD
   Temp: COM
   Voltage: COM

   Click OK button and will create a .stf file.
   
   
5. Simulation Using Actel library
   This will open the design architect to compile the structural VHDL generated by actmap and simulate.

   % setenv QUICKHDL /opt1/actel/lib/vtl/95/qhdl/quickhdl.ini
   % ln -s $QUICKHDL .
   % da

6. Simulation with Extracted Delay
   This will open the qhsim by,

   % qhsim -sdftyp set_time_str.sdf

Acknowledgement

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