Final Report

Final Report for Digital Thermostat (Revised Version)

Abstract

In the EE552 Design, a Digital Thermostat is designed, built, and tested. The programmable device compares the room temperature to a user-specified temperature to control the operations of a furnace. While the device can be programmed to maintain roon temperature at different level during different times of a day, the user can perform a manual override at any time. The Digital Thermostat has six 7-segment displays. The first four diplays the current time and the remaining two displays the user specified temperature.

The design is implemented on an ACTEL A1020B-PL68C field programmable gate array. Programming is carred out in VHDL and converted into netlist and fuse filed by ACTEL design tools. QuickHDL of Mentor Graphics is also used to carry out both pre-synthesis and post-synthesis simulations. The design takes up 485 of 547 logic modules on the ACTEL A1020B chip.

A prototype system, including the necessary external circuitries, is built on an SK-10 board for easy debugging and testing. The system behaved the same as the simulation excepts that one output pin does not function at all. It is believed that the failure was casued either by static electricity or by defect in the FPGA.

This report includes details about the design, simulation and testing. Documentation such as VHDL codes is also included.

IC Data
Overview
Design Details
Design Verification
IC Test
Conclusion

IC Data

Generatl Description

The Digital Thermostat is a user-programmable device that regulates room temperature by comparing the actual ambient temperature with a user-specified temperature. When the room temperature falls below the user-specified temperature, the Digital Thermostat signals a furnace to turn on until the room temperature rises to the user-specified level. A digital 24-hr clock is incorporated into the design to provide a program function, which allows the user to specify a desired room temperature at 9:00am and 7:00pm. At any other time, the user can manually change the desired temperature to any value between 0³C and 31³C. The program function makes the Digital Thermostat ideal for home and office applications. For example, in an office environment, the device can be programmed to keep the temperature low at night in order to save energy. In the morning, when higher temperatures are desired, the furnace will be turned on automatically.

Features

Implemented on an ACTEL A1020B-PL68C field programmable gate array.

Displays time and user-specified temperature on seven-segment displays.

Indicator light for furnace operations.

Energy-saving program function.

Key Specifications

Supply Voltage 4.75V to 5.25V

Clock Frequency 120Hz

I/O Sink/Source Current þ20mA (absolute maximum)

Logic Blocks

Entity	Comb. Modules(modules)	Area (modules)	Longest Path(ns)
temperature comparator	13	15	48.7
clock	94	168	95.6
decoder 3(temperature)	22	22	77.8
7-segment selector 1	75	92	57.4
decoder 2(minute)	35	35	106.1
7-segment selector 2(temperature)	26	41	29.2
temperature controller	53	63	117.8
decoder 1(hour)	19	19	70.6
overall	367	48.5	205.6

Overview

The Digital Thermostat system has two basic functions: to display time (in 24 hour format) and to control the operations of a furnace. It reads the current ambient temperature and compares the current temperature to a user-specified desired temperature (programmable). Whenever the current temperature falls below the desired temperature, the thermostat signals the furnace to start. Later, when the ambient temperature rises and becomes the same as the desired temperature, the thermostat turns off the furnace. A program function allows two desired temperatures, dtemp1 and dtem2. At 9:00 am, the thermostat sets the desired temperature to dtemp1. Ten hours later, at 7:00 pm, the thermostat sets the desired temperature to dtemp2. The desired temperatures can be configured using eight DIP switches; four for dtemp1 and the other four for dtemp2. Each group of four switches represents a 4 bit binary number. The desired temperatures are the sum of 15(base 10) and the binary numbers. For example, if the first group of switches reads "on-off-off-off" then dtemp1 = 15(base 10) + 1000(base 2) = 23(base 10). At any time of the day, the user can temporarily change the desired temperature by pressing the buttons labeled "up" and "down". The desired temperature, however, will go back to dtemp1 and dtemp2 at 9:00 am and 7:00 pm respectively.

Time and desired temperature are displayed by 7-segment displays, in two separate cycles. Each cycle is 1/30 sec long. In each cycle, each digit of time (4 digits) or desired temperature (2 digits) is sequentially displayed. Moreover, an LED indicates whether the furnace is turned on or off. In addition to the features described above, a reset button is available to reset time to 00:00 and desired temperature to 25³C.

Pin Name	Type	Function
reset	in (pust button)	Resets and initializes the system.
clock	in	System clock.
up	in (push button)	Push button for incrementing desired temperature.
down	in (push button)	Push button for decrementing desired temperature.
pgm1	in (four switches)	Sets the desired temperature at 7:00 pm.
pgm2	in (four switches)	Sets the desired temperature at 7:00 pm.
ctemp	in (five pins)	Receives the current temperature.
furnace	out	Turns on or turn off the furnace.
time_segment	out (7 pins)	Outputs time to 7-segment.
time_segment	out (7 pins)	Outputs temperature to 7-segment.
time_sel	out (4 pins)	Selects which of the four digits of time to display.
time_sel	out (2 pins)	Selects which of the two digits of temperature to display

Design Details

ACTEL A1020B-PL68C

The programming of the FPGA is accomplished in VHDL. The system includes 8 entities and the top-level entity "thermostat". The following is a list of entity declarations of the VHDL codes, followed by explanatory notes.

inc_time (clock)

entity inc_time is

port(
clock, reset: in std_logic;
check1, check2 : out std_logic;
min_out : out std_logic_vector(5 downto 0);
hr_out : out std_logic_vector(4 downto 0)
);
end inc_time;

This entity is the clock and it increments time. Its outputs are hour and minute of time and is sent to 7-segment selector 1 through decoder 1 and decoder 2. At 9:00 am and at 7:00 pm, it sends out a signal to the temperature controller through ports "check1" and "check2" respectively. These signals enable the temperature controller to carry its program function.

temp_disp (7-segment selector 2)

entity temp_disp is

port(
clock, reset : in std_logic; digit1 : in std_logic_vector(1 downto 0); digit0 : in std_logic_vector(4 downto 0); segment : out std_logic_vector(6 downto 0); sel : out std_logic_vector(1 downto 0)
);
end temp_disp;

This entity takes in two binary words from decoder 3, or "tdecoder". Each word represents a digit of the desired temperature. It then decodes each digit into a 7-bit word and output the result to a 7-segment display. It also selects which 7-segment displays the 7-bit word.

tdecoder (decoder 3)

entity tdecoder is

port (
input: in std_logic_vector(4 downto 0); tenth: out std_logic_vector(1 downto 0); one: out std_logic_vector(4 downto 0)
);
end tdecoder;

It takes in a 5-bit binary number that represents desired temperature. It then separates the 5-bit number into "tenth" and "one" (two binary numbers which represent the two digits of the temperature). For example, if 111112 is the input, then the decoder will return 112 for the first digit and 000012 for the second digit.

hdecoder/ mdecoder (decoder1/2)

entity hdecoder is

port (
input: in std_logic_vector(4 downto 0); tenth: out std_logic_vector(1 downto 0); one: out std_logic_vector(4 downto 0)
);
end hdecoder;

entity mdecoder is

port (
input: in std_logic_vector(5 downto 0); tenth: out std_logic_vector(2 downto 0); one: out std_logic_vector(5 downto 0)
);
end mdecoder;

They have the same functions as "tdecoder", but they are used for decoding the hour and minute of current time.

time_disp (7-segment selector 1)

entity time_disp is

port(
clock, reset : in std_logic; digit3 : in std_logic_vector(1 downto 0); digit2 : in std_logic_vector(4 downto 0); digit1 : in std_logic_vector(2 downto 0); digit0 : in std_logic_vector(5 downto 0); segment : out std_logic_vector(6 downto 0); sel : out std_logic_vector(3 downto 0)
);
end time_disp;

This entity is similar to "temp_disp". It is larger than "temp_disp" since each value of time consists of four digits.

set_temp (temperature controller)

entity set_temp is

port(
clock, up, down, reset : in std_logic; chk1, chk2 : in std_logic; prg1, prg2 : in std_logic_vector(3 downto 0); dtemp : out std_logic_vector(4 downto 0)
);
end set_temp;

It controls desired temperature. At 9:00 am it receives a signal from "inc_time" and it turns the desired temperature into (1510 + dtemp1). At 7:00 pm it receives another signal to turn the desired temperature into (15-10 + dtemp2). At all other times, the user can temporarily change the desired temperature by pressing "up" or "down".

comp_temp (temperature comparator)

entity comp_temp is

port(
clock, reset : in std_logic; dtemp, ctemp : in std_logic_vector(4 downto 0); furnace : out std_logic
);
end comp_temp;

"comp_temp" takes in the desired temperature and compares it with the current temperature. It turns on the furnace only if current temperature is smaller than desired temperature.

thermostat

entity thermostat is

port(
clock, reset : in std_logic; up, down : in std_logic; pgm1, pgm2 : in std_logic_vector(3 downto 0); ctemp : in std_logic_vector(4 downto 0); furnace : out std_logic; time_segment : out std_logic_vector(6 downto 0); temp_segment : out std_logic_vector(6 downto 0); time_sel : out std_logic_vector(3 downto 0); temp_sel : out std_logic_vector(1 downto 0)
);
end thermostat;

This is the top level entity that combines all the entities listed above.

External Temperature Sensor/Thermometer

The Digital Thermostat has five input pins for the ambient temperature. It requires that the temperature be a five-bit binary number. Although such a parallel interface makes the design simple, it is not compatible with most commercial digital thermometer chips. The reason is that most digital thermometer chips on the market have serial interfaces in order to reduce pin usage. In addition, serial interfaces may vary with different manufacturers. Therefore, in order for the Digital Thermostat to have the ability to work with different thermometer chips, it is decided that an extra (and smaller) FPGA will be incorporated into the system. The extra FPGA will receive temperature data serially from a thermometer chip and pass the data to the Digital Thermostat in a parallel manner.

The National Semiconductor "LM75 Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface" is a thermometer chip that is suitable for the Digital Thermostat. It utilizes an I2C Bus Interface of Philips Corporation. The following VHDL entity is designed to allow the LM75 to communicate with the Digital Thermostat:

entity LM75 is

port(
clock, enable :in std_logic; SDA :inout std_logic; SCL :out std_logic; ctemp :out std_logic_vector(4 downto 0)
);
end LM75;

In the entity, "SDA" is the data bus on which temperature is read from the LM75, while "SCL" is the clock signal received by the LM75. When the entity receives an "enable" signal, it signals the LM75 to begin a read cycle. At the end of the cycle, the entity outputs the temperature data as a five-bit binary number, at port "ctemp". The complete VHDL code for this entity can be found in the "Appendix" section.

Due to time constraints, we did not program the entity onto an FPGA and thus could not incorporate the LM75 thermometer chip into the overall system. For testing and demonstration purposes, switches are connected to the temperature inputs of the Digital Thermostat in order to simulate changes in room temperature.

Clock

The system clock for the Digital Thermostat is chosen to be 120Hz. The reason behind this choice is related to the 7-segment displays used. In the design, the time is displayed by a group of four 7-segments, in cycles. In each cycle, each of the four 7-segments is turned on sequentially and there are 30 cycles in each second. This way, the 7-segments will appear to be constantly turned-on in human eyes. In order to achieve such effect, the clock frequency will need to be at least 4(30)Hz=120Hz.

If a crystal oscillator is used, the system clock will likely be in the megahertz range. This kind of clock frequency will likely be too high for the 7-segments. Further tests will be required to determine if the 7-segments can glow bright enough under high clock frequencies. At first, a "clock divider" circuit was planned. The circuit was to have a counter. When the counter counts to a certain value, it will reset and generate a second, slower clock pulse. Depending on the size of the counter, the "clock divider" approach can generate a second clock signal that is much slower than the system clock. Unfortunately, two problems are associated with this approach. On the one hand, the counter can take up much valuable space on the FPGA if the system clock is much faster than the new clock signal. On the other hand, the new (slower) clock signal is not connected to a clock buffer. Depending on the total number of entities the new clock is fed to, fan-out problems will likely occur. As a result, the "clock divider" approach was dropped.

For ease of design and implementation, a 555-timer is used to generate the system clock. It is relatively easy to design a 555-timer circuit that produces a pulse train with periods in the millisecond range. The main drawback of the 555-timer approach is that it is difficult to achieve a high timing accuracy with RC components. As a result, the real-time clock of the Digital Thermostat will not be very accurate. The schematic of the 555-timer circuit can be found in the Appendix section.

Push Buttons

The Digital Thermostat has three push button inputs: "up", "down", and "reset". At each rising clock edge, the system checks the level of the each button to determine if actions need to be taken. The "up" and "down" buttons can be directly affected by the clock frequency. For example, if the user pushes and holds the "up" button, the "up" input at the FPGA will stay high for several clock edges. With a system clock at 120Hz, even if the user only lightly touches the "up" button, the desired temperature will be incremented several times, instead of once.

In order to correct this problem, a monostable 555-timer circuit is connected between each push button and the corresponding FPGA input. While the system clock period is 8.33ms, each monostable circuit is designed to produce a 5ms pulse when a button is pushed. As a result, the desired temperature will be incremented or decremented only once when "up" or "down" is pushed. In addition, a large capacitor is required for debouncing. A complete schematic of the monostable 555-timer circuit is included in the Appendix section.

7-Segment Displays (common anode)

There are two groups of pins connected to each group of 7-segment displays - the "selector" pins and the "segment" pins. Each "selector" pin is connected to the common anode of a 7-segment display, while each "segment" pin is connected to the corresponding cathodes. Recall that the displays are sequentially turned on during normal operations. When a display has to be turned on, a "selector" pin will go high to supply current to the common anode. At the same time, a logic value "0" at the "segment" pin will allow current flow and turn on the diode. Similarly, a logic value "1" at the "segment" pin will turn off the diode.

In a lab, it is determined that a 200W resistor between a "selector" pin and a common anode will limit the current flow at the "selector" pin to 17.25mA. The purpose of the resistor is to ensure that the maximum I/O current of the FPGA is not exceeded.

Power Supply

The FPGA needs a 5V power supply. Since it is awkward to bring a variable DC power supply (the ones used in the undergraduate labs) with the Digital Thermostat, an LM2905 voltage regulator is incorporated into the system.

The LM2905 has three pins: input, ground, and output. The input can accept voltages between (approximately) 7V and 20V. When it receives input in this range, its output pin stays at 5V, with adequate accuracy and stability for the FPGA. (The FPGA used in this project requires a 5Vþ5% VCC.) Therefore, a small AC/DC adapter, as found in toys and small electrical appliances, can be used for the Digital Thermostat.

Synthesis

When the VHDL coding was completed, we tested various features of the ACTMAP synthesis tool. The netlist for the entity "disp_temp" was synthesized with under different configurations. The following table summarizes the results we obtained.

Longest Path	Comb.	Area	flatten	effort	map style	max fanout
58.9	69	86	no	high	area	16
164.1/td>	298	315	no	low	area	16
164.1	298	315	no	low	NoOpt	16
164.1	298	315	yes	low	NoOpt	16
58.9	69	86	yes	high	NoOpt	16
55.8	75	92	yes	high	NoOpt	8
55.8	75	92	yes	med	NoOpt	8
47.5	80	97	yes	med	Speed	8
47.0	71	88	yes	med	Speed	24

In general, size of the resulting netlist depends very much on the "effort" put into the synthesis. The netlists produced with "high" efforts are much small than those produced with "low" efforts, but no significant difference was observed between "high" and "medium" effort for our design. Flattening the netlist has no direct effect on the size of the netlist. Moreover, lowering fanout will increase the area of the netlist and lengthen the longest path. Map style "area" and "no-opt" produced netlists that are similar in size and longest path. However, "speed" can decrease the length of the longest path, at the expense of increasing the number of modules used. We also tried the "Netlist Optimizer":

Longest Path	Comb.	Area	effort	map style
47.6	71	88	high	upoptimized
50.7	68	85	high	Area
45.4	76	93	high	Speed
59.4	69	86	high	upoptimized
50.7	68	85	high	Area
44.6	76	93	high	Speed

The results suggest that the Netlist Optimizer can result in slightly more efficient usage of logic modules or shortened longest path. However, each result is accomplished on the expense of the other. The revised design did not need area optimization to be fit onto the chip. Moreover, since speed is not a large concern for the Digital Thermostat, speed optimization was not used

Design Verification

The back-annotated simulation has been carried out and it is found that the system performs as expected. The following is selected simulation results that covers all aspects of system operations.

In the simulation, the clock period is set to 8ms, which is reasonably close to the proposed system clock period of 8.33ms. To make simulation more efficient, a few modifications were made to the VHDL codes prior to the simulation. Instead of counting to 7200, the entity "inc_time" counts up to only 18 before it increments minute. Moreover, the program times in "set_temp" were changed from 09:00 and 19:00 to 02:00 and 03:00.

Note:

inputs	Full Name
/clock	system clock
/reset	reset button
/up	up button
/down	down button
/pgm1	dtemp1(temperature of program 1)
/pgm2	dtemp2(temperature of program 2)
/ctemp	current temperature(input)

outputs	Full Name
/time_segment	7-bit word displayed on 7-segment (for time)
/time_sel	selects which of the four digits of time on 7-segment to display
/time_segment	7-bit word displayed on 7-segment (for desired temperature)
/time_sel	selects which of the two digits of temperature on 7-segment to display
/furnace	furnace turns on when high, turns off when low.

waveform1 (normal operations)

Initially, the system is reset. Furnace turns off, 7-segments are set to display tenth digit of hour and temperature. Desired temperature is set to 25³C and time is set to 00:00.

Current temperature (ctemp on waveform) is set to 25³C. Since current and desired temperature are the same, the furnace stays off after reset.

Current temperature is changed to 24³C at 90ms. Now current temperature is lower than desired temperature (25³C), furnace turns on.

"down" is pressed between 110 to 120ms. Desired temperature changes to 24³C. Furnace turns off at 124ms since desired temperature now equals current temperature.

"up" is pressed between 145 to 150ms. Desired temperature changes to 25. Furnace turns on at 156ms.

waveform2 (time increment)

Time displayed on 7-segment turns from 00:59 to 01:00.

waveform3 (up button) -- current temperature at 25³C

The desired temperature starts at 25³C. "up" is pressed and stays high. At the next falling edge, furnace turns on. Desired temperature increases until it reaches 31³C. Then desired temperature becomes 0³C and subsequently 1³C. At the falling edge after 0³C, the furnace turns off.

waveform4 (down button) -- current temperature at 25³C

The desired temperature starts at 1³C. "down" is pressed and stays high. Desired temperature decreases to 0³C, then becomes 31³C, and finally 30³C. At the falling edge after desired temperature becomes 31³C.

waveform5 (program 1) -- current temperature at 25³C

When time changes from 01:59 to 02:00, program 1 changes desired temperature from 25³C to (1510 + 11112) ³C = 30³C. Furnace turns on since desired temperature > current temperature.

waveform6 (program 2) -- current temperature at 25³C

When time changes from 02:59 to 03:00, program 2 changes desired temperature from 30³C to (15 + 00002) ³C = 15³C. Furnace turns off since desired temperature < current temperature.

IC Test

Since the operations of the system are relatively simple and since the complexity of the system is not high, it is determined that the most efficient way of testing the FPGA will be to incorporate it into an overall system and check the functions/operations of the system.

Immediately after the test had begun, it was found that pin 8, "time_sel(1)", stayed inactive at 0V. The pin is designed to be connected to the common anode of the 7-segment responsible for the tenth digit of minute. Therefore, the 7-segment could not light up. Recall that the simulation was completely successful. Since the FPGA was handled with care and group members constantly "grounded" themselves before making contact with it, the chip was probably defective. One possible "work-around" to this problem is to use a 3-input NOR gate. Recall that the "selector" pins in a group of 7-segments go high sequentially. When "time_sel(1)", the dead pin, is supposed to have a logic "1", the other three selector pins have logic "0"s. Therefore, when the other pins are connected to the inputs of a 3-input NOR gate, the output of the NOR gate will have a logic "1" whenever its inputs are all zero, i.e., whenever pin 8 should supply current to the common anode.

The following is a summary of the tests that are performed. The system behaved exactly as expected, except for pin 8, "time_set(1)". In the summary below, the results are obtained with the "work-around" described above:

When the power is turned on, random (out of range) numbers appeare on the 7-segment displays. "Reset" is pressed, current time reads "0000" and desired temperature reads "25".
Current temperature is initially set to "25". Furnace indicator light is off because current temperature is the same as desired temperature.
Current temperature is changed to "24". Furnace light turned on since desired temperature is greater than current temperature.
"Down" is pressed once and desired temperature reads "24". Furnace light turns off since desired temperature now equals current temperature.
"Up" is pressed once. Desired temperature reads "25". Furnace light turns on again.
The "up" button is pressed several times. The desired temperature increases to "31" then becomes "00". When desired temperature is at "00" the furnace light turns off (current temperature is still at "24").
The "down" button is pressed. The desired temperature changes from "00" to "31". Furnace light turns on.
DIP switches for program 1 are initially set to "off-off-off-off". Nine hours later, when time reads "0900" desired temperature becomes 11112+00002=1510 and the 7-segment display shows "15". Furnace light is off.
DIP switches for program 2 are initially set to "on-on-on-on". When time is "1900" the desired temperature becomes 11112+11112=3010 and the 7-segment display shows "30". Furnace light turns on again.
During the test, the clock increments correctly. For example, "0059" turns into "0100" and "2359" turns into "0000".

Conclusion

The actual implementation of the Digital Thermostat differs a lot from the original plan. Although the original design was synthesized by ACTMAP successfully and went through post-synthesis simulation without errors, it was much too large to be fitted onto an ACT1 family FPGA. As a result, the original design became subject to major revisions. In order to make the design small enough to be programmed onto an A1020B chip, the design had to be made less flexible and less interactive. Moreover, the interface circuitry for a digital thermometer chip had to be taken out. As a result, another FPGA will have to be programmed if a digital thermometer is to be incorporated into system.

Besides the space constraint of the FPGA, time constraint was the biggest difficulty faced by the members of this group. Given more time, a number of improvements and modifications can be made to the system. However, the project is considered to be successful in general and it provided the group members with valuable experience.

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