A Smart Home Security System is designed to provide you with the most security for your house. Like many home securities system today, the Smart Home Security System not only provides the basic security feature, but also it is able to communicate with the user.

Today, although many houses have already installed alarm security system, they are still broken in by the thieves. This can be explained mostly by human factor. People tend to totally rely on the machine. What happens if they forget to close one door or window before arming the security? This would leave a big opening for the thieves.

The central idea behind this Smart Home Security System is to attack the above question. Whenever the user tries to arm the Smart Security, system will check if there is an open door or window in your house. If this is the case, the system will identify you on the display the location of these opened door or window. For example, front door opens, an LED will be lighted to indicate the front door and the display will show "opens".

For this design, we will mainly use VHDL to implement the function of the Smart Home Security System and be finally embedded in ACTEL ACT™ 1 Series FPGA (A1020B, 68pin PLCC) chip. Also, some output pins in the chip are used for testing and debugging purpose. The details will be described later in the report.

The main design of this Smart Home Security System will be embedded in ACTEL ACT1 Series Field Programmable Gate Arrays (FPGAs) chip. Due to the size of this design, we choose the package of A1020B, 68Pin PLCC. This chip will provide us with 547 logic modules and 57 user I/O pins.

Our design uses 527 out of the 547 logic modules, which are about 96% of the whole chip. For the I/O pins, this design uses all 57 user I/O pins; description of user I/O pin is listed below:

　

Pin Name	Meaning
Vcc	connected to power source
Gnd	connected to ground
Mode	connected to ground
Window (1:0)	2 input signals correspond to front and back windows
Door (1:0)	2 input signals correspond to front and back doors
Light (3:0)	4 output signals correspond to window(1:0) and door(1:0)
Led_out(6:0)	7 output signals for 7-segment display
Switch(3:0)	4 input signals to control the system.
Enter	1 input signal to load values in the switch(3:0)
Police	1 output signal to inform police station or security co.
Buzzer	1 output corresponds to the alarm buzzer
Reset	1 input signal to reset the whole system
Clock	1 input signal to provide the clock to the system
Timestart	1 output signal to acknowledge the start of 30 second countdown
Lcd_data (7:0)	8 output signals to LCD display
Lcd_select	1 output signal to LCD for register selection
Lcd_rw	1 output signal to LCD for read/write
Lcd_e	1 output signal to LCD for enable
System Testing Pins
ms (3:0)	4 output signals to show the state machine of Main Controller module
ps (4:0)	5 output signals to show the state machine of Password Checker module
c_test (1:0)	2 output signals to show the control buses
s_test (2:0)	3 output signals to show the signal buses
control_c (1:0)	2 input signals to control the control buses
control_s (2:0)	3 input signals to control the signal buses

Table 1. Meaning for each layout pin

Refer to Figure 1 for the complete layout of the I/O pins.

The main physical components of the system are the ACT™ 1 (A1020B, 68Pin PLCC) package with 57 user I/O pins. The rest of the hardware is specified as follows:

　

Components	Usage
4 Switch	User input switches
4 Switch	Represent doors and windows
4 LED (door)	Indication of which doors or windows are opened
1 LED (time)	Indication of 30 seconds countdown has started
1 LED (police)	Indication of alarm signal has sent to police station
1 buzzer	Indicate someone has violated the security system
LCD (LM16255)	Output message
7-segment (MAN3472A)	Output message
1 voltage regulator　　　　　　　 (LM 7805CK)	Provide the system with a regulated 5 volts.

Table 2. Component involved in the Smart Home Security System and their usage.
　

Note:
The LCD has built in controllers. It receives an eight-bit code representing a letter or number. The LCD is solely for communicating with the user and will only receive data from the Actel chip. This message has been hard coded in the LCD display module

The voltage regulator will take any input voltage between 5-10 volt and convert to 5 volts for the whole system.

When the system is turned on, the user is prompted by a small LCD display to either change the password or arm the security system (this is the main menu).
　

1. Change Password　　　　　　 　　　　 2. Arm system

　

If the user wishes to change the password, he or she will be prompted to enter the present four digit password on the switch and press enter button.

　

Enter Password

　　

If the password entered is not the correct present password then the LCD will display "Password Mismatch" then return to main menu.

　

Not Match

　

If the password is correct, the user will be prompted to enter a new four digit.
　
　

Enter new password

　
　
The user will be required to confirm the new password by entering it again.

　

Re-enter new password

　　
If the values are not equal, it will go back to the main menu and do the process again.

　
　

Not Match

　　

If the values are equal, the LCD will display "Password Changed" and return to the main menu.

　

Password Changed

　　
　

1. Change Password　　　　　 　　　　 2. Arm system

　

If the user wishes to arm security, he or she will be prompted to enter the present four digit password.
　

Enter Password

　　
If the password entered is not the correct present password then the LCD will display "Not Match" and return to the main menu. If the password is, system will begin checking for open doors or windows. If any open doors or windows are detected, the LCD will display "opens") and user will look at the door leds to determine which door is still opened.

　

opens

　
The user must close all windows and doors and then repeat the process. The system will recheck the password and recheck for open doors and windows. The process is repeated until all windows and doors are closed.

Once everything is closed, the LCD will display "No door opens" and a thirty second countdown will start.

　

No door opens

　　

The user must vacate the building within these 30 seconds and close the door behind him or her. After 30 seconds the system is fully armed and begins checking for open doors or windows. If an opening is detected, the system begins a thirty second countdown and checks if the present password has been entered.

　

Enter Password

　
If the password is entered correctly, the system disarms. If the password is not entered or is entered incorrectly, the countdown continues. After 30 seconds a signal is sent to the police station or security company via telephone cable.

• Door Checker
• Switch Decoder
• LCD Display
• Password Checker
• Main Controller

In this section, we will also discuss and demonstrate the logic flow of each module.

Door Checker Module

The Door Checker module checks for any opened doors and windows. If an opening is detected, a signal is sent to the Main Controller via "d" bus. Figure 3 shows the flow logic of this module. The following is the entity for Door Checker:

library ieee;
use ieee.std_logic_1164.all;

entity door_check is

port( window,door : in std_logic_vector (1 downto 0);
d : out std_logic_vector(3 downto 0);
clock : in std_logic);

These meaning to pins are as follows:

　

Pins	Signal Meaning
Window(1:0)	input signal represents front and back window respectively
Door(1:0)	input signal represents front and back door respectively
D(3:0)	4 output signals correspond to window(1:0) and door(1:0)
Clock	input signal from system clock

Table 3. I/O pins for Door Checker module and their meaning

entity switch_decoder is

port (switch : in std_logic_vector (3 downto 0);
enter, clock, reset : in std_logic;
d : out std_logic_vector(3 downto 0);
ready : out std_logic );

These meaning to pins are as follows:
　

Pins	Signal Meaning
Switch(3:0)	4 user input switch to control the system
Enter	1 input signal to load the value of switch(3:0)
D(3:0)	4 output signals correspond to switch(3:0)
Clock	input signal from system clock
Ready	1 output signal corresponds to Enter input pin

Table 4. I/O pins for the Switch Decoder module and their meaning

The LCD Display module simply receives the signal messages sent from the Main Controller module (via status bus) and decodes this signal messages into Human readable English messages in the LCD display. Inside the LCD Display module, it contains a look up table (LUT) that has all the messages needed for the Smart Home Security System. Again, due to the area in ACT™ 1 FPGA problem, only the acronym will be displayed. The following table shows the meanings of the control bus and the acronym.

This status bus is 7-bits wide. The reason of the 7-bits is mainly for backup purpose. Just in case if the LCD display module is not working, this 7-bits control bus is also connected to the 7-segment (common anode) display. It is still able to communicate to user.

　

status bus	intended LCD message	acronym	7-segment display
0000001	Change Password Arm Security	1C:2A	0
1001111	Enter Password	E.P.	1
0010010	Not Matched	NOT M	2
0000110	Enter New Password	E.N.P	3
1001100	Re-enter New Password	RE-EP	4
0100100	Password Changed	PW-CH	5
1100000	Open	OPEN	6
0001111	No Door Opens	N.D.O.	7
0000000	Initialize LCD Signal	---	8
0001100	Time Out	T.OUT	9

Table 5. The Look-up-table in the LCD display module

The following shows the entity for the LCD display module:

entity LCD is port(

clock : in std_logic;

reset : in std_logic;

lcd_data : out std_logic_vector( 7 downto 0 );

lcd_select : out std_logic;

lcd_rw : out std_logic;

lcd_e : out std_logic;

status : in std_logic_vector( 6 downto 0 ) );

end LCD;

The lcd_data, lcd_select, lcd_rw, and lcd_e are used to control the operation of the LM16255 LCD unit.

(LM 16255 User Manual has included in Appendix.)

Password Checker Module

The Password Checker Module has four modes of operation: command, change password, arm security mode and key press mode. First, the Main Controller (via c bus) puts the Password Checker into a command mode to receive any input command. If the command received (via p bus) is either case 1) Change Password or case 2) Arm Security, otherwise ignored, it returns a handshaking signal (via s bus) to the Main Controller. Then, Main Controller will put the Password Checker into different mode strictly based on the incoming handshaking signal. Refer to Table 6 for details. If the Password Checker is in change password mode, it checks if the password, which was entered, is correct. It will compare the entered password to the stored present password and return a signal to the Main Controller module indicating if there was a match or not. Similar idea is for arm security mode. In addition, when the Password Checker is in the key press mode, it ignores any values in the switches and returns a signal if a button is pressed or not. The following shows the entity of Password Checker module:

entity passwd_checker is

port (

p : in std_logic_vector(3 downto 0);

c : in std_logic_vector(1 downto 0);

s : out std_logic_vector(2 downto 0);

clock : in std_logic;

ready : in std_logic;

reset : in std_logic;

pstate: out std_logic_vector(4 downto 0));

end passwd_checker;

　

S(2:0)	Meaning
000	1. Change Password
001	2. Arm Security
010	Enter pressed, ignore switch
011	Password entered is correct
100	Password entered is incorrect
110	Password Saved
111	Normal

Table 6. Meaning of S bus

The following shows the entity of the Main Controller module:

ENTITY main_control IS

PORT (

lcd_control : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ;

pc_s : IN STD_LOGIC_VECTOR(2 downto 0) ;

clock : IN STD_LOGIC ;

police : OUT STD_LOGIC ;

dc : IN STD_LOGIC_VECTOR(3 downto 0) ;

pc_control : OUT STD_LOGIC_VECTOR(1 downto 0) ;

light : out std_logic_vector(3 downto 0);

reset : IN STD_LOGIC ;

timestart : OUT STD_LOGIC;

time_is_up : IN STD_LOGIC;

mstate : out std_logic_vector(3 downto 0)) ;

END main_control ;

　

pc_control bus	Meaning
00	Command mode
01	Change Password mode
10	Arm Security mode
11	Key press mode

Table 7. Meaning of pc_control bus.

Design Verification (Simulation)

In this verification section, we will mainly simulate the top level of the Smart Home Security System. As well, we will demonstrate them using the post-layout (extracted or back-annotated) simulation. All the test cases we choose follow the "Decision Coverage Testing" approach, which is to cover enough test cases such that each decision has a true and false outcome at least once.

Figure 3 shows a flow diagram for the Smart Home Security System. All the simulation test cases will be primarily based on this flow diagram

Table 8 explains the meaning of each signal in the system.

Note:

In the test case 1, we have included the output waveform to the LCD display to demonstrate the whole picture of the Smart Home Security System.

However, in the simulation time diagram for test case 2-6, we ignore the output to the LCD display for the reason of simplifying the output waveform, so that it is easier to show the system functionality.

Flow Diagram

Table 7. Signal Meaning in Timing Diagram

　

Signal Name	Meaning
reset	reset of the whole system
clock	clock
enter	Enter button
switch (3:0)	4 input switches
time_is_up	after the 30 seconds count down, a pulse will be generated in the time_is_up signal
timestart	timestart will be asserted when we want to start to time the 30 seconds
police	police will be asserted when the person is unable to disarm the security system
c (1:0)	c = control signals generated by the Main Controller module. Main Controller module uses this ‘c’ signal to put the Password Checker module in different mode (command or password mode).
s (2:0)	s = status signals generated by the Password Checker module. PC module uses ‘s’ signal to communicate to the Main Controller. For example, s = 011 means a correct password has entered.
ms (3:0)	state machine for the Main Controller module
ps (4:0)	state machine for the Password Checker module
window (1:0)	front window and back window
door (1:0)	front door and back door
led_out (6:0)	Two meaning　　　　　　　 control signal for the LCD display module the output signal for the 7-segment display
light (3:0)	indication of which doors or windows are opened
lcd_select	LCD select
lcd_rw	LCD Read / Write
lcd_e	LCD Enable
control_s	Just in case if the signal ‘s’ is not working for some reason, we can force input manually.
control_c	similar idea for the signal ‘c’.

　

IC Testing

After all aspects of the design have simulated correctly, we blow the fuses on an FPGA. All cases have been tested and results turn out as expected. However, only two testing results will be recorded because it takes lot of time to record one test case. The following are the test vectors we have used to test our prototype system and results are recorded as follow:

　

switch(3:0)	enter	window	door	police	buzzer	led_out(6:0)	reset	time_is_up
0000	0	00	10	0	0	0000000	0	0
0000	1	00	10	0	0	0000000	0	0
0000	1	00	10	0	0	0000000	0	0
0000	1	00	10	0	0	0000000	0	0
0000	1	00	10	0	0	0000000	0	0
0000	1	00	10	0	0	0000000	0	0
0001	0	00	10	0	0	0000001	0	0
0001	1	00	10	0	0	1001111	0	0
0001	0	00	10	0	0	1001111	0	0
0001	0	00	10	0	0	1001111	0	0
1111	1	00	10	0	0	1001111	0	0
1111	0	00	10	0	0	1100000	0	0
1111	1	00	10	0	0	1100000	0	0
1111	0	00	10	0	0	1100000	0	0
1111	0	00	10	0	0	0000001	0	0

　

light	s_test	ms	c_test	ps	timestart	lcd_data(7:0)	lcd_select	lcd_rw	lcd_e
0000	100	0001	00	11000	0	00100000	1	0	1
0000	100	0001	00	11000	0	00100000	1	0	1
0000	100	0001	00	11000	0	00110000	1	0	1
0000	100	0001	00	11000	0	00110000	1	0	0
0000	100	0001	00	11001	0	00000110	0	0	1
0000	100	0001	00	11001	0	00000110	0	0	0
0000	111	0001	00	00001	0	00110010	1	0	0
0000	001	0001	00	00001	0	00110010	1	0	0
0000	001	0011	10	00010	0	01000001	1	0	1
0000	001	0011	10	00010	0	00000010	0	0	1
0000	001	0011	10	00011	0	01000101	1	0	0
0000	011	0011	10	00101	0	00100000	1	0	0
0000	111	1000	00	00111	0	01000111	1	0	0
0000	010	1000	00	01001	0	01010000	1	0	1
0000	010	1000	00	01001	0	01010000	1	0	1

Table 8. Recorded test result for test case 1

Note: After this intensive testing, I suspect that there may be a broken pin inside the FPGA. I have shown in the shaded region, the bit 3 always reads "zero". This can account the reason why my LCD unit cannot display letter. It is because this "00110000" should be "00111000" which is the initializing data for the LCD unit. If the LCD has not got initialized, it won’t be able to display anything.

After the above testing, we do another testing to verify result. Thing turns out the same that in the Smart Home Security System, every signal generated is as expected; however, only bit 3 of the lcd_data bus still remains zero. This result in the LCD unit does not function.

Test 2

　

switch(3:0)	enter	window	door	police	buzzer	led_out(6:0)	reset	time_is_up
0000	0	00	00	0	0	0000000	0	0
0000	1	00	00	0	0	0000000	0	0
0000	1	00	00	0	0	0000000	0	0
0000	1	00	00	0	0	0000000	0	0
0000	1	00	00	0	0	0000000	0	0
0000	1	00	00	0	0	0000000	0	0
0001	0	00	00	0	0	0000001	0	0
0001	1	00	00	0	0	1001111	0	0
0001	0	00	00	0	0	1001111	0	0
0001	0	00	00	0	0	1001111	0	0
1111	1	00	00	0	0	1001111	0	0
1111	0	00	00	0	0	1100000	0	0
1111	1	00	00	0	0	1100000	0	0
1111	0	00	00	0	0	1100000	0	0
1111	0	00	00	0	0	0000001	0	0

　

light	s_test	ms	c_test	ps	timestart	lcd_data(7:0)	lcd_select	lcd_rw	lcd_e
0	100	0001	00	11000	0	00100000	1	0	1
0	100	0001	00	11000	0	00100000	1	0	1
0	100	0001	00	11000	0	00100000	1	0	1
0	100	0001	00	11000	0	00100000	1	0	0
0	100	0001	00	11001	0	00010000	0	0	1
0	100	0001	00	11001	0	00010000	0	0	0
0	111	0001	00	00001	0	00110010	1	0	0
0	001	0001	00	00001	0	00110010	1	0	0
0	001	0011	10	00010	0	01000001	1	0	1
0	001	0011	10	00010	0	00000010	0	0	1
0	001	0011	10	00011	0	01000001	1	0	0
1	011	0011	10	00101	0	00100000	1	0	0
1	111	1000	00	00111	0	01000111	1	0	0
1	010	1000	00	01001	0	01010000	1	0	1
1	010	1000	00	01001	0	01010000	1	0	1

Table 9. Recorded test result for test case 2

Clock Design – External Circuit

The controller will need to have a clock input to make this design a synchronize design. The input clock pulse will be at 1000Hz, which will be supplied by an oscillator externally. The reason that the oscillator is external, and not designed into the Actel chip is because the limiting modules that the chip contain. To design an oscillator inside the chip would mean to further cut down on the features of this design, so we decided to add an oscillator outside to maximize the features that this controller could have. After careful consideration, we decided to use a 555-timer chip for the clock input. The detail of design will be shown below.

Figure 4. Circuit for a 1000Hz clock

Calculations

(Ra+Rb)*C ln 2 = 1ms

let C = 10nF

(Ra+Rb) C ln 2 = 1ms

(Ra+Rb)*10nF*ln 2 = 1ms

Ra + Rb = 144.3kohm

Rb*ln 2*C = 0.95 ms

Rb (10nF) * ln 2 = 0.95 ms

Rb = 137.1kohm

Therefore, Ra = 144.3k – 137kohm = 7.2 kohm

Timer

If space is allowed, more features such as 30 seconds timer can also be included inside the FPGA. The following is the VHDL for the 30 seconds timer (assume 1khz clock):

library ieee;

use ieee.std_logic_1164.all;

entity timer is

port (clock, timestart : in std_logic;

time_is_up : out std_logic);

end timer;

architecture time of timer is

begin

timer_logic: process(clock,timestart)

variable timecounter : integer := 0;

begin

if (clock = '1' and clock'event) then

if timestart = '1' then

if timecounter < 30000000 then

timecounter := timecounter + 1;

elsif timecounter = 30000000 then

time_is_up <= '1';

end if;

elsif timestart = '0' then

timecounter := 0;

time_is_up <= '0';

end if;

end if;

end process;

end time;

(This timer module takes approx. 200 logic modules)

KeyPad

Again, if we were allowed to use a larger FPGA, we can change the input device from switch to keypad. This change would provide us with more security to the system. It is because using switch would leave a trace for next person. If the user enter the password, he/she forgets to turn the switch to some other value. This would leave the password opened for the next user. It is very unsafe. We have included the VHDL code for the keypad decoder on page 33. This keypad decoder takes approx. 160 logic modules.

Speed VS Area

Under Actmap, there is a speed VS area options. We have tried to compile the whole design under different options. Results are recorded as follows:

Area

　

Module Name	Estimated Worst Delay (ns)	Area (modules)
Door Checker	0.00	0
Switch Decoder	8.20	8
Password Checker	91.50	174
Lcd Display	95.40	168
Main Controller	75.50	161
Overall System	97.90	532

　

Speed

　

Module Name	Estimated Worst Delay (ns)	Area (modules)
Door Checker	0.00	0
Switch Decoder	8.20	8
Password Checker	89.90	175
Lcd Display	79.30	194
Main Controller	60.50	175
Overall System	103.00	579

　

When comparing individual module under speed option, the estimated worst delay seems reasonable as opposed to the area trade off. It gets more modules as the worst delay is shortening. However, when the system combines together, speed option turns out that it has more modules for more time. VERY STRANGE! Therefore, I definitely choose area option for my design.

Conclusion

In the course of design, I have learned and gained a lot of experience by actually completing this project "Smart Home Security System" myself. At the design stage, I have faced a major setback, which results from my partner dropped the course. Therefore, I carry on this project with 2 people workload. Many things have to be discovered and tried out myself. Later, when I am the first time and try to "actmapw" the design. Amazing thing happens. It turns out that the design is far more modules than the Actel chip can support. Then, I start to cut things down. At that time, I really learn how to design and write VHDL code efficiently under Actmapw.

After I redesign and every thing seems all right under Actmapw, then I think that life would be a bit easier from here on. However, life does not always turn out nicely. When I try back-annotated the design, the even worst thing happens and nothing seems to work. Then, I recognize two things. One is that MSB and LSB are reversed. Two, I start to insert more testing I/Os for the design. Following step by step approach, I finally fix all the problems and have a workable piece of the Smart Home Security System.