-- sample_keeper
-- This is an interface to memory, it cycles
--	through states for gestapo control over what is
--  on the address bus when we select the memory lines
--  from this module.
--  we don't hook up to the data bus as such, but
--  rather an address bus.
-- The reason this is so elaborate is that this
-- module is not the only one controlling the memory,
-- in fact we may have solved digital delay here.
--
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;


entity sample_keeper is
	port(
		reset,
		clock,
		read, 
		free_base, 
		write 
			: in std_logic;

		addrbus : out std_logic_vector(9 downto 0);

		s_read, 
		s_write, 
		read_complete, 
		write_complete 
			: out std_logic
				
 		);
end sample_keeper;


architecture behavioural of sample_keeper is


signal address : std_logic_vector(9 downto 0);
signal address_delay : std_logic_vector(9 downto 0);
type write_state_type is ( output_address, write_data, complete);
signal write_state,next_write_state : write_state_type;
type read_state_type is ( increment_address, output_address, complete);
signal read_state,next_read_state : read_state_type;

begin
	
	addrbus<=address;
	write_cycle : process (write_state, write, reset)

	begin

case write_state is

	when output_address =>

		write_complete 	<='0';
		s_write		<='0';
		if write = '1' then
			next_write_state <= write_data;
		end if;
				
	when write_data =>

		s_write <= '1';
		next_write_state <= complete; 

	when complete =>

		s_write			<='0';
		write_complete 		<= '1';	
		next_write_state <= output_address;

end case;
		
end process write_cycle;


write_state_register : process

begin
		
wait until (clock = '1' and clock'event); 

	write_state <= next_write_state;
		if reset = '1' then
			write_state <= output_address;
		end if;

end process write_state_register; 


read_cycle : process
	--(address,address_delay,free_base, read_state, read, reset)

begin

case read_state is

	when increment_address =>

		read_complete	<= '0';
		s_read		<= '0';
		if read = '1' then
			address_delay <= address+"0000000001";
			next_read_state <= output_address;
		end if;

	when output_address => 
	
		address 	<= address_delay;
		s_read		<= '1';
		next_read_state <= complete;	


	when complete =>

		read_complete   <= '1';
		s_read		<= '1';
		if free_base = '1' then
			next_read_state <= increment_address;
			s_read <= '0';
		end if;

end case;				


wait until (clock = '1' and clock'event);
	
	if reset = '1' then
		address <= "0000000000";
	end if;
		--this does seem a bit loopy what are the implications
		--of these possibly contradicting concurrent statements

end process read_cycle;


read_state_register : process

begin

wait until (clock = '1' and clock'event);
				
	read_state <= next_read_state;
	if reset = '1' then
		read_state <= increment_address;
	end if;

end process read_state_register; 

end behavioural;