-- peak_keeper
-- This is an interface to memory, it cycles
--	through states for gestapo control over what is
--  on the address bus when we select the memory lines
--  from this module.
--  we don't hook up to the data bus as such, but
--  rather an address bus.
--  We have two separate wrap around counters, one for writing, one for reading
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity peak_keeper is
	port(
		reset,
		clock,
		read,  
		next_peak,
		free_base,
		write
			: in std_logic;
			
		addrbus 
			: out std_logic_vector(7 downto 0);
		
		s_read, 
		s_write, 
		read_complete, 
		write_complete 
			: out std_logic
				
 		);
end peak_keeper;


architecture behavioural of peak_keeper is

signal w_address,r_address : std_logic_vector(7 downto 0);
signal w_address_delay,r_address_delay : std_logic_vector(7 downto 0);
type write_state_type is (increment_address, output_address, write_data, complete);
signal write_state,next_write_state : write_state_type;
type read_state_type is ( increment_address, output_address, complete);
signal read_state,next_read_state : read_state_type;

begin

address_cycle : process(r_address,w_address,write,read,clock,reset)

	begin
		if reset = '1' then		
			addrbus <= "00000000";
		elsif write = '1' then
			addrbus<=w_address;
		elsif read = '1' then
			addrbus<=r_address;
		end if;

end process address_cycle;


write_cycle : process(w_address_delay,w_address,write_state, write, reset)

	begin
		write_complete 	<='0';
		s_write		<='0';
		if reset = '1' then
			w_address <= "00000000";
		end if;

case write_state is

	when increment_address =>
	
		if write = '1' then
			w_address_delay <= w_address+"00000001";
			next_write_state <= output_address;
		end if;
			
	when output_address =>

		w_address 	<= w_address_delay;	
		s_write       	<= '0';
		next_write_state <= write_data;
			
	when write_data =>
					
		s_write			<='1';	
		next_write_state 	<= complete;
 
	when complete =>
					
		write_complete <= '1';
		next_write_state <= increment_address;

end case;		

end process write_cycle;


write_state_register : process

begin
		
wait until (clock = '1' and clock'event);
	write_state <= next_write_state;
	if reset = '1' then
		write_state <= increment_address;
	end if;

end process write_state_register; 


increment_read : process

begin

wait until (clock='1' and clock'event);
	if reset = '1' then
		r_address <= "00000001";
	elsif next_peak = '1' then
		r_address <= r_address + "00000001";
	end if;
	
end process increment_read;
		
		
read_cycle : process(free_base, read_state, read, reset)

begin

case read_state is

	when increment_address =>

		read_complete	<='0';
		s_read  	<='0';
		if read = '1' then
			next_read_state <= output_address;
		end if;

	when output_address =>

		s_read		<= '1';
		next_read_state <= complete;	
				

	when complete =>

		read_complete 	<= '1';
		s_read		<= '1';
		if free_base = '1' then
			next_read_state <= increment_address;
		end if;

end case;				

end process read_cycle;


read_state_register : process

begin

wait until (clock = '1' and clock'event);

	read_state <= next_read_state;
	if reset = '1' then
		read_state <= increment_address;
	end if;

end process read_state_register; 

end behavioural;