set_attribute {"clock"} "pad_location" -type string "U1" /* Global Clock PGCK4 */
   set_attribute {"reset"} "pad_location" -type string "H17" /* pin 2 Proto A */

   set_attribute {"memory_enable"} "pad_location" -type string "F1" /* pin 20 SRAM */
   set_attribute {"memory_read"} "pad_location" -type string "E2" /* pin 22 SRAM */ 
   set_attribute {"memory_write"} "pad_location" -type string "B1" /* pin 27 SRAM */

   set_attribute {"DA_write"} "pad_location" -type string "N17" /* pin 21 Proto A */  
   set_attribute {"AD_clock"} "pad_location" -type string "P17" /* pin 24 Proto A */
   set_attribute {"AD_sample"} "pad_location" -type string "R18" /* pin 22 Proto A */

   set_attribute {"address_line[0]"} "pad_location" -type string "N3" /* pin 10 SRAM */ 
   set_attribute {"address_line[1]"} "pad_location" -type string "P1" /* pin 20 SRAM */  
   set_attribute {"address_line[2]"} "pad_location" -type string "P2" /* pin 20 SRAM */  
   set_attribute {"address_line[3]"} "pad_location" -type string "P3" /* pin 20 SRAM */
   set_attribute {"address_line[4]"} "pad_location" -type string "R1" /* pin 20 SRAM */ 
   set_attribute {"address_line[5]"} "pad_location" -type string "R2" /* pin 20 SRAM */ 
   set_attribute {"address_line[6]"} "pad_location" -type string "T1" /* pin 20 SRAM */ 
   set_attribute {"address_line[7]"} "pad_location" -type string "T5" /* pin 20 SRAM */ 
   set_attribute {"address_line[8]"} "pad_location" -type string "D1" /* pin 20 SRAM */ 
   set_attribute {"address_line[9]"} "pad_location" -type string "D2" /* pin 20 SRAM */
   set_attribute {"address_line[10]"} "pad_location" -type string "E3" /* pin 20 SRAM */
   set_attribute {"address_line[11]"} "pad_location" -type string "U4" /* pin 20 SRAM */
   set_attribute {"address_line[12]"} "pad_location" -type string "T6" /* pin 20 SRAM */   
   set_attribute {"address_line[13]"} "pad_location" -type string "C1" /* pin 20 SRAM */
   set_attribute {"address_line[14]"} "pad_location" -type string "E1" /* pin 20 SRAM */ 



   set_attribute {"from_AD[0]"} "pad_location" -type string "V15" /* pin 40 Proto A */
   set_attribute {"from_AD[1]"} "pad_location" -type string "U14" /* pin 39 Proto A */ 
   set_attribute {"from_AD[2]"} "pad_location" -type string "T13" /* pin 38 Proto A */  
   set_attribute {"from_AD[3]"} "pad_location" -type string "V16" /* pin 37 Proto A */
   set_attribute {"from_AD[4]"} "pad_location" -type string "U15" /* pin 36 Proto A */
   set_attribute {"from_AD[5]"} "pad_location" -type string "T14" /* pin 35 Proto A */
   set_attribute {"from_AD[6]"} "pad_location" -type string "U18" /* pin 34 Proto A */
   set_attribute {"from_AD[7]"} "pad_location" -type string "P16" /* pin 33 Proto A */


   set_attribute {"to_processor[0]"} "pad_location" -type string "A13" /* To FPGA2 tune_bus[0] */
   set_attribute {"to_processor[1]"} "pad_location" -type string "A14" /* To FPGA2 tune_bus[1] */ 
   set_attribute {"to_processor[2]"} "pad_location" -type string "A12" /* To FPGA2 tune_bus[2] */  
   set_attribute {"to_processor[3]"} "pad_location" -type string "A17" /* To FPGA2 tune_bus[3] */
   set_attribute {"to_processor[4]"} "pad_location" -type string "C4" /* To FPGA2 tune_bus[4] */
   set_attribute {"to_processor[5]"} "pad_location" -type string "B5" /* To FPGA2 tune_bus[5] */
   set_attribute {"to_processor[6]"} "pad_location" -type string "B6" /* To FPGA2 tune_bus[6] */
   set_attribute {"to_processor[7]"} "pad_location" -type string "B9" /* To FPGA2 tune_bus[7] */


   set_attribute {"super_tune_bus[0]"} "pad_location" -type string "N2" /* pin 11 SRAM */
   set_attribute {"super_tune_bus[1]"} "pad_location" -type string "N1" /* pin 12 SRAM */  
   set_attribute {"super_tune_bus[2]"} "pad_location" -type string "M1" /* pin 13 SRAM */   
   set_attribute {"super_tune_bus[3]"} "pad_location" -type string "L3" /* pin 15 SRAM */
   set_attribute {"super_tune_bus[4]"} "pad_location" -type string "L2" /* pin 16 SRAM */ 
   set_attribute {"super_tune_bus[5]"} "pad_location" -type string "L1" /* pin 17 SRAM */
   set_attribute {"super_tune_bus[6]"} "pad_location" -type string "K2" /* pin 18 SRAM */ 
   set_attribute {"super_tune_bus[7]"} "pad_location" -type string "K1" /* pin 19 SRAM */ 


   set_attribute {"check_for_noise"} "pad_location" -type string "A6" /* To FPGA2 enable_noise_gate */ 
   set_attribute {"enable_tuner"} "pad_location" -type string "A5" /* To FPGA2 enable */  
   set_attribute {"read_sample_done_pin"} "pad_location" -type string "A10" /* To FPGA2 sample_ready_for_process */
   set_attribute {"reset_slave"} "pad_location" -type string "A11" /* To FPGA2 reset */
   set_attribute {"start_process"} "pad_location" -type string "A8" /* To FPGA2 begin_process */
 
   set_attribute {"emo_done"} "pad_location" -type string "A9" /* From FPGA2 process_finished */