EE 552 98f 98-9-28 - press reload

Lab 3: Static Timing Analysis and Pipelining

Please read the updated requirements for lab assignments.

In this lab, you will use static timing analysis to find the performance of circuits and to tune a pipelined circuit. Static timing analysis finds the slowest path through a circuit without simulation or considering specific data, hence the word "static". Static timing analysis can be used to measure delays, setup/hold times and minimum clock periods.

The use of the MAX+PLUS II "Timing Analyzer" is described.

Exercise

When things aren't going right...

When things aren't going right and the error messages aren't very meaningful, try these desperate measures:

Narrow down what's causing the mystery problems. Comment out large chunks of VHDL code, including recent additions, until the error goes away.
See if your code compiles in another tool such as Mentor Graphics.
Quit maxplus2 and restart it.
Some of your configuration files (e.g. *.acf) may have become corrupted. Move your *.vhd files to a new directory and recompile.

Delay Analysis

Compile the adder you used in the exercise of Lab 2. Find out how many of the chip's logic cells were used by this adder, double-click the "rpt" icon below the fitter, then search "^F Total logic". You will find a result that looks like:
Total logic cells used: 7/1152 ( 0%)

Now run static timing analysis. Select:

MAX+plus II -> Timing Analyzer ...

Analysis -> Delay Matrix

Start

Where is the critical path (from what signal to what signal)?
What kind of adder is implemented?

Read the online documentation for the maxplus2 Timing Analyzer.

Help -> MAX+plus II Table of Contents

Analysis of Clocked Circuits

The timing analyzer can also be used for clocked circuits:

Try these two tools on a synchronous counter with enable, such as the one in lab 1.

Lab

Part A: Growth of Delay

Measure the minimum clock period for at least three different sizes of counters (16, 32, 64 bits) and use this to estimate the clock period as a function of the number of bits in the counter. (Hand in only calculation and function.)

Part B: Reducing Critical Paths

Carry-save arithmetic does not fully propagate carries, but rather, stores results in a redundant format with 2 bits representing each bit of the result. VHDL code for a carry-save adder is provided as an example.

Design a carry-save counter.

Again, express the minimum clock period as a function of the number of bits in the counter.

This carry-save arithmetic technique can also used in fast multipliers.

Part C: Tuning Pipelines

Design an unsigned multiplier (8-bit multiplicands, 16-bit product) so as to minimize the following cost function:

cost(#logicCells, latency, throughput) = #logicCells * 1/cell + latency * 0.01/ns + 1000000MHz / throughput Use lpm_mult -- read the online documentation. Do not use any EAB's (embedded array blocks = memory) in this lab. Include the library with:

library lpm;
use lpm.lpm_components.all;

Your design should include lpm_mult and pipeline registers before and after it. The data input and output of your multiplier must be registers in order for registered-performance timing analysis to provide a report for your entire circuit. Measure the total number of logic cells in the design. Throughput is the maximum clock frequency (MHz). We will define latency as the number of pipeline register stages, not counting the first one, (alternatively, the number of pipeline stages in lpm_mult plus one) times the minimum clock period.

Hints:

The version of maxplus2 on the workstations produces faster designs than the student version
The lpm_mult component definition in the online documentation has syntax errors. Some strings have not been quoted.

This is a class competition. Supply the following:

Appropriate text from the fitting report.
Timing analyzer results and brief simulator output from maxplus2
Note which version of maxplus2 you are using
Cost calculation (put a box around the answer)

Place the cost on your title page as well.