Lab 3: VHDL Synthesis and Extracted-Timing Simulation

You will be using the Altera MAX+PLUS II tools (maxplus2 is available on the CAD suns, nyquist HPs or sign out  CD-1 for installation on your own PC).

This lab has two parts: an exercise that is not handed in, in which you will become familiar with the tools, and a lab that will be
submitted for marking, in which you will create your own design.

Labs are to be done individually.  Please feel free to consult the professor, the T.A. or your fellow students for help with tools
and concepts.
 

Hints

Interfaces -> VHDL netlist reader settings...
and select VHDL-1993

Options -> Snap to Grid

Assign -> Device ...
select device family: FLEX10K from the first list
deselect show only fastest speed grades
select EPF10K20RC240-4 from the second list

Exercise (do not hand in)

Part 1: Become Familiar with MAX+PLUS II

% mkdir ~/ee552/lab3
% cd ~/ee552/lab3
% maxplus2 &
or possibly
% /opt1/maxplus2/bin/maxplus2 &

Part 2:  Simulate a Simple Combinational Circuit

--------------------
-- Adder

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity adder is
        generic(adder_width :positive := 4);
        port(a,b: in std_logic_vector(adder_width-1 downto 0);
                sum: out std_logic_vector(adder_width downto 0)
        );
end adder;

architecture behavioural of adder is
begin

        sum <= a + b;

end behavioural;
 
 

Lab

Part 1: Thoughts on Simulation

1. Exactly how many pairs of previous inputs and new inputs would you have to test to exhaustively determine the maximum delay between all combinations of inputs?
2. Making reasonable assumptions about the implementation of the adder, what sets of inputs might produce the maximum delay?

Part 2: Simulating Synchronous Circuits

Use the following naming for the 7 segments:

----0
|  |
|5 |1
----6
|  |
|4 |2
----3

1. What is the minimum clock period for which the circuit still performs correctly through all states (values of counter)?
2. What is the worst-case delay from clock to output?
3. What is the worst-case delay from reset to output?

Part 3: Configuring FPGAs/CPLDs - Bonus

Assign the pins according to this procedure.  Use the FLEX pushbuttons (FLEX_PB1 & 2) for input and FLEX 7-segment LEDs (FLEX_DIGIT) for output as described in the UP1 documentation.

Now download the configuration to the chip.  After resetting, you'll see that pushing the button used as the clock input causes the counter to increment more than once.  Record how many clock edges are detected for pushing and for releasing the clock button (reset inbetween).

1. What is the maximum and the average count for pressing the button?
2. What is the maximum and the average count for releasing the button?
3. Show this system to your TA during the lab (if possible).

Part 4: Behavioural VHDL

/* create a table of squares without using multiplication */
#include <stdio.h>
#define UPPER_LIMIT 15

main(){
int n, nsquared, sum, oldsum;

sum = 0;
oldsum = 0;
for( n=0; n<=UPPER_LIMIT; n++) {
    oldsum = sum;
    sum += n;
    nsquared = sum + oldsum;
    printf("%d squared is %d\n", n, nsquared);
}
exit(0);
}

1. What is the minimum clock period for correct operation?
2. Why would you want to think of clever ways to avoid performing multiplication in hardware?