-- The top file of a hierarchy

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- the following line should be commented out when running actmap
-- use ieee.std_logic_unsigned.all;

entity top is port (
   a, b, c : in std_logic;
   f : out std_logic;
   m, n : in std_logic_vector(7 downto 0);
   sum : out std_logic_vector(8 downto 0)
);
end top;

architecture mixed of top is

component myand2 port(
   a, b : in std_logic;
   f : out std_logic
);
end component;

for all: myand2 use entity work.myand2(functional);

signal g : std_logic;

begin

firstand:  myand2 port map ( a => a, b => b, f => g );
secondand: myand2 port map ( a => g, b => c, f => f );

sum <= m + n;

end mixed;