-----------------------------------------------------
-- FIFO Buffer Module Control Path
-- File : fifoctrl.vhdl
-- Author : Noah Aklilu
-- Created : June 22, 1998
-- Description : Implements a FIFO buffer using 
--               MCM60256A SRAM chips or an internal
--               register
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.all;

-- Entity Declaration
entity fifo_ctrl is
	port (
				pop : in std_logic;
				push : in std_logic;
				popack : out std_logic;
				pushack : out std_logic;
				latch : out std_logic;
				toggle : out std_logic;
				full : in std_logic;
				empty : in std_logic;
				clk : in std_logic;
				reset : in std_logic
			);

end entity;

----------------------------------------------------------------
-- Simple Architecture
-- This is the architecture that uses the internal register
-- and is much simpler in design than the SRAM based fifo buffer
----------------------------------------------------------------

architecture simple of fifo_ctrl is

type statevariable is ( start, pop1, pop2, push1, push2);

signal state : statevariable;

begin

	main : process(clk) is

	begin
		
		if reset = '1' then

			state <= start;

------------------------------------
-- This can be changed to rising_edge
-- depending on which synthesises 
-- better
------------------------------------

		elsif ( clk'event and clk = '1') then

			case state is

				when start =>

---------------- Beginning of a push operation

					if	push = '1' and empty = '1' then

						state <= push1;

---------------- Beginning of a pop operation

					elsif pop = '1' and full = '1' then

						state <= pop1;

					else

						state <= start;

					end if;

				when pop1 =>

					state <= pop2;

				when pop2 =>

					state <= start;

				when push1 =>
	
					state <= push2;

				when push2 =>
	
					state <= start;

				when others =>

					state <= start;

			end case;
	
		end if;
	
	end process;


	with state select
		latch <= '1' when push1,
					'0' when others;

	with state select
		toggle <= '1' when push2 | pop2,
					 '0' when others;

	with state select
		popack <= '1' when pop1 | pop2,
					 '0' when others;

	with state select
		pushack <= '1' when push2 | push1,
				     '0' when others;
		
end architecture;