USING MENTOR FOR VHDL

1. Before You Start Design Architect
2. Creating a vhdl file
3. Compilation and Simulation
4. Command Line Tools
5. Working in Other Labs Besides CEB 531

Before You Start Design Architect

shell> cd ~
shell> mkdir ee552
shell> cd ee552
shell> mkdir lab1
shell> cd lab1

Now for Design Architect, we need to set some environment variables so
type :

shell> setenv MGC_WD `pwd`
shell> setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini

Note that `pwd` is enclosed in back quotes which should be above the
TAB key on your keyboard.

You might want to put  "setenv QUICKHDL $MGC_HOME/lib/quickhdl.ini" in your .login
file which is located as yourhomedir/.login

Because MGC_WD uses the pwd command, it will grab the current directory (to see what
I mean type "pwd" in a shell window), so you want to be in your working directory before you
type it in, so don't put it in your .login because it grabs your homedir instead of your working
directory.  Instead you can put this in a script that sits in your project directory like this one,
once you have saved the script, you will need to make it executable type:

shell> chmod 700 mymentorscript
 

Creating a vhdl file

1. Start Mentor's Design Architect by typing "da" at the command prompt.
2. Once da has started, you will see a palette of icons to the right, click on the "Open VHDL" icon
3. The "Open VHDL" dialog window will popup, in "VHDL Source Name" field type in the name of your source

e.g. "homedir/ee552/lab1/mylab.vhd"
You can click on the "Navigator" button to see a directory listing from which you can make a choice
4. Click "OK"
5. You should now have the text editor popup a window with your file
6. With your text window highlighted choose the "Set Compiler Options" choice from the palette on the right
   Alternative: Use the menu choice "Compile->Set Options"
7. This will pop a "Set VHDL Compilations Options"

In the Work Library field : set it to yourhomedir/ee552/lab1/work
Select the "Explicit Scoping", "VHDL 93" and "Constraint Checking" options
8. Click "OK"
9. Now you can start typing in your VHDL code into the text window

Compilation and Simulation

Compiling and running qhsim

1. Start da and open your VHDL file, make sure you have set the work library correctly using the "set Compiler Options" palette choice or appropriate menu choice (see above)
2. Click on the "Compile" option on the palette to the right
   Alternative: Click on the "Compile" menu and select "Compile"
3. When Mentor is compiling it will popup a window with any errors or else it will say "Quickhdl compilation completed successfully"
   Errors in your vhdl code can be highlighted by double-clicking on the respective error in the compile window
4. Start at the bottom of your design hierarchy and compile each file in your design in this manner
5. When you are finished compiling, click on the "QuickHDL" menu choice and select "Simulate"
6. Click "OK"
7. A "Startup" window will popup, select the Entity and respective Architecture you want to test 
   If you don't see your entity in the window, then you probably don't have your work directory setup properly, go back and check this.
8. Click "Load"
9. qhsim will now load your design and you will have a command window in front of you.
10. type in the command window "wave /*" to load the toplevel signals in your design or type "wave -r /*" to load ALL the signals in your design
11. this will popup the wave window and your signals will visible

Running the Simulation

QHSIM> force reset 1

If you are using a clock and you want to set your clock input to a repeating signal use the syntax:
"force my_clock first_value first_delay, second_value second delay -r clock_period", for example

QHSIM> force clock 0 0, 1 20 -r 40

This gives a signal that is initially '0' and changes to '1' after 20ns, repeating every 40ns.

Once you have forced your [input] signals to their initial values, you can start the simulation by typing "run"
in the command window or click on the "RUN" button.

You will notice the simulation will only run for 100ns, this is the default run length, you can change this by
clicking on the "Options" menu of the command window and select "Properties", then change the "default
run" value to the length you desire.  You can also change the run length while using the "run" command by
using the syntax "run run_length", for example

QHSIM> run 500

This will run for 500 ns.
 

Loading or Restarting a Simulation

To load a new simulation without using  Design Architect ("da"), you can do so by clicking on the
"File" menu of the command window and select "Load New Design".  This will take you back to
the "Startup" window that you first saw when you started qhsim from da.

Restarting a Simulation:

To restart a simulation which will clear your forced signals and waveforms, you can type "restart -f"
in the command window.  Alternatively you can click on the "File" menu and select "Restart design" and
click "OK" after that.
 

Recommendations

• Don't be afraid to see what some of the other menus in the qhsim do
• If you find yourself having to force a lot of signals for initialization or something similar, you can use
  a command script to do that for you.  The format is whatever you would type in at the command window
  and you can run it by clicking on the "File" menu and select "Execute Command File", then select your
  script file and click on "Execute".
• Every time you compile, "da" saves your vhdl file so if you are making temporay changes to your file either 
  make backups or comment out code instead of deleting it.  With a large project you might even want to use
  RCS (version control software).
• If your simulation uses complex signal inputs (or long ones) you might want to consider writing a testbench 
  for your project, look at Ashendan's Designer's Guide to VHDL for examples.

Command Line Tools

Creating a WORK library:

If  you haven't already, you will need to create a WORK library, this is normally a directory in your project/lab directory.
Before you do this make sure you are in your working directory and then type

shell> qhlib work

Do not use "mkdir" to create this directory, this directory has special properties which qhlib needs to set.

Compiling a file:

Once you have created the work directory, you can compile your file by typing:

shell> qvhcom myfile.vhd

if you are using VHDL93, you need to specify -93 as a compile option like this

shell> qvhcom -93 myfile.vhd

The compiler will automatically put your entity into the work directory (unlike "da" which needs explicit definition).

Simulating a design:

The simulator is started by typing

shell> qhsim

and it will come up similar to if you had started it from "da".

Because the simulator needs "X", you will need to be physically in front of an X terminal with the correct options (such
as the DISPLAY environment variable) set.  If it starts, complains and then dies this is probably why.
 

Working in Other Labs Besides CEB 531

If you want to work at home, you can login and use the command line tools with the exception of qhsim using a telnet or xterm.

If you have a high speed connection such as ISDN or a cable modem, look at this appnote from last year about setting
up a X server to run "da" from home.  This appnote is aimed at Windows users, but UNIX  (or Linux, *BSD)  users
should be able to glean something from this.

Working in other UNIX Labs

If you can't work in CEB 531 because it is in use or full, then you can work one of the other UNIX labs such as:

CEB 540  (Gecko Lab) : This lab has "da" locally available, but your files from CEB 531 are not available here so you will need
to copy them across using FTP.  You can also login into one of the CEB 531 machines (cabXX.labs.ualberta.ca) and work
remotely using the command line tools including qhsim.

CAB 311 (Hinton Lab) : This lab does not have "da", but you can login into CEB 531 and use the command line tools including qhsim.