/*
 * pattern.v
 *
 * Modified from pattern.vhd for EE552 lab 6
 * by Kris Breen
 * February 6, 2003
 *
 */

module pattern(reset, clock, bitstream, match, matches);
parameter tallywidth = 7;
input reset, clock, bitstream;
output match;
output [tallywidth-1:0] matches;
reg match;

reg [1:0] state, next_state;

always
begin
	match <= 0;

	case (state)
		0:	begin  // sawnull
				if (bitstream == 1)
					next_state <= 1;  // saw1
				else
					next_state <= 0;  // sawnull
			end
		1:	begin  // saw1
				if (bitstream == 1)
					next_state <= 2;  // saw11
				else
					next_state <= 0;  // sawnull
			end
		2:	begin  // saw11
				if (bitstream == 0)
					next_state <= 3;  // saw110
				else
					next_state <= 0;  // saw11
			end
		3:	begin  // saw110
				next_state <= 0;  // sawnull
				if (bitstream == 1)
					match <= 1;
			end
	endcase
end

always @(posedge clock or posedge reset)
begin
	if (reset == 1)
		state <= 0;
	else
		state <= next_state;
end

// Structural Verilog
// Instantiate a counter
count matchcounter(.enable(match), .aclr(reset), .clock(clock), .q(matches));
	defparam matchcounter.counterwidth = tallywidth;

endmodule