/*
 * count.v
 *
 * Modified from count.vhd for EE 552 lab 6
 * by Kris Breen
 * February 6, 2003
 *
 */

module count(enable, aclr, clock, q);
parameter counterwidth = 4;
input enable, aclr, clock;
output [counterwidth-1:0] q;
reg [counterwidth-1:0] q;

always @(posedge clock or posedge aclr)
begin
	if (aclr == 1)
		q <= 0;
	else if (enable == 1)
		q <= q + 1;
end

endmodule